©2013 Silicon Storage Technology, Inc.

DS20005054C

04/13

5

2 Mbit SPI Serial Flash

SST25VF020B

Data Sheet

Memory Organization

The SST25VF020B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32

KByte overlay blocks and 64 KByte overlay erasable blocks.

Device Operation

The SST25VF020B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.

The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is

accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).

The SST25VF020B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference

between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in

Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is

high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock

signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.

Figure 3: SPI Protocol

1417 SPIprot.0

MODE 3

SCK

SI

SO

CE#

MODE 3

DON'T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

MODE 0

HIGH IMPEDANCE

MSB

MSB