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AD9944KCPRL Datasheet(PDF) 6 Page - Analog Devices |
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AD9944KCPRL Datasheet(HTML) 6 Page - Analog Devices |
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6 / 20 page  AD9943/AD9944 Rev. B | Page 6 of 20 TIMING SPECIFICATIONS CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11. Table 5. Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period tCONV 40 ns DATACLK High/Low Pulse Width tADC 16 20 ns SHP Pulse Width tSHP 10 ns SHD Pulse Width tSHD 10 ns CLPOB Pulse Width1 tCOB 2 20 Pixels SHP Rising Edge to SHD Falling Edge tS1 10 ns SHP Rising Edge to SHD Rising Edge tS2 16 20 ns Internal Clock Delay tID 3.0 ns DATA OUTPUTS Output Delay tOD 9.5 ns Pipeline Delay 9 Cycles SERIAL INTERFACE Maximum SCK Frequency fSCLK 10 MHz SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Falling Edge to SDATA Valid Hold tDH 10 ns 1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. |
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