AD5302ARMZ datasheet(15/24 Pages) AD

15 / 24 page

AD5302/AD5312/AD5322

Rev. D | Page 15 of 24

SERIAL INTERFACE

The AD5302/AD5312/AD5322 are controlled over a versatile,

3-wire serial interface, which operates at clock rates up to 30 MHz

and is compatible with SPI, QSPI, MICROWIRE, and DSP

interface standards.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide (see Figure 30 to Figure 32).

Data is loaded into the device as a 16-bit word under the control

of a serial clock input, SCLK. The timing diagram for this

operation is shown in Figure 2. The 16-bit word consists of four

control bits followed by 8, 10, or 12 bits of DAC data, depending

on the device type. The first bit loaded is the MSB (Bit 15),

which determines whether the data is for DAC A or DAC B.

Bit 14 determines if the reference input is buffered or unbuffered.

Bit 13 and Bit 12 control the operating mode of the DAC.

Table 6. Control Bits

Bit

Name

Function

Power-On Default

A/B

0: Data Written to DAC A

N/A

1: Data Written to DAC B

BUF

0: Reference Is Unbuffered

1: Reference Is Buffered

PD1

Mode Bit

PD0

Mode Bit

BIT 15

(MSB)

BIT 0

(LSB)

PD0

D7D6

D5D4D3D2D1

PD1

BUF

DATA BITS

A/B

Figure 30. AD5302 Input Shift Register Contents

BIT 15

(MSB)

BIT 0

(LSB)

PD0

D7D6D5D4D3D2D1D0

PD1

BUF

DATA BITS

A/B

Figure 31. AD5312 Input Shift Register Contents

BIT 15

(MSB)

BIT 0

(LSB)

PD0

D7D6D5D4

D3D2D1D0

PD1

BUF

DATA BITS

A/B

D11 D10

Figure 32. AD5322 Input Shift Register Contents

The remaining bits are DAC data bits, starting with the MSB and

ending with the LSB. The AD5322 uses all 12 bits of DAC data,

the AD5312 uses 10 bits and ignores the 2 LSB. The AD5302 uses

eight bits and ignores the last four bits. The data format is straight

binary, with all 0s corresponding to 0 V output, and all 1s

corresponding to full-scale output (VREF – 1 LSB).

The SYNC input is a level-triggered input that acts as a frame

synchronization signal and chip enable. Data can only be

transferred into the device while SYNC is low. To start the serial

data transfer, SYNC should be taken low observing the minimum

SYNC to SCLK active edge setup time, t4. After SYNC goes low,

serial data is shifted into the device’s input shift register on the

falling edges of SCLK for 16 clock pulses. Any data and clock

pulses after the 16th are ignored, and no further serial data

transfers occur until SYNC is taken high and low again.

SYNC can be taken high after the falling edge of the 16th SCLK

pulse, observing the minimum SCLK falling edge to SYNC

rising edge time, t7.

After the end of serial data transfer, data is automatically

transferred from the input shift register to the input register of

the selected DAC. If SYNC is taken high before the 16th falling

edge of SCLK, the data transfer is aborted and the input

registers are not updated.

When data has been transferred into both input registers, the

DAC registers of both DACs can be simultaneously updated by

taking LDAC low.

LOW POWER SERIAL INTERFACE

To reduce the power consumption of the device even further,

the interface only powers up fully when the device is being

written to. As soon as the 16-bit control word has been written

to the part, the SCLK and DIN input buffers are powered down.

They only power up again following a falling edge of SYNC.

DOUBLE-BUFFERED INTERFACE

The AD5302/AD5312/AD5322 DACs all have double-buffered

interfaces consisting of two banks of registers—input registers and

DAC registers. The input register is connected directly to the input

shift register and the digital code is transferred to the relevant input

Access to the DAC register is controlled by the LDAC function.

When LDAC is high, the DAC register is latched and the input

DAC register. However, when LDAC is brought low, the DAC

This is useful if the user requires simultaneous updating of both

DAC outputs. The user can write to both input registers

individually and then, by pulsing the LDAC input low, both

outputs update simultaneously.

These parts contain an extra feature whereby the DAC register

is not updated unless its input register has been updated since

the last time that LDAC was brought low. Normally, when

LDAC is brought low, the DAC registers are filled with the

contents of the input registers. In the case of the AD5302/

AD5312/AD5322, the part only updates the DAC register if

the input register has been changed since the last time the

DAC register was updated, thereby removing unnecessary

digital crosstalk.

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