PIC24FJ64GA006 datasheet(97/258 Pages) MICROCHIP

97 / 258 page

 2005-2012 Microchip Technology Inc.

DS39747F-page 97

PIC24FJ128GA010 FAMILY

8.0

OSCILLATOR

CONFIGURATION

The oscillator system for PIC24FJ128GA010 family

devices has the following features:

• A total of four external and internal oscillator options

as clock sources, providing 11 different clock modes

• On-chip 4x PLL to boost internal operating frequency

on select internal and external oscillator sources

• Software-controllable switching between various

clock sources

• Software-controllable postscaler for selective

clocking of CPU for system power savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

A simplified diagram of the oscillator system is shown

in Figure 8-1.

FIGURE 8-1:

PIC24FJ128GA010 FAMILY CLOCK DIAGRAM

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 6. “Oscillator”

(DS39700)

the

“PIC24F

Family

Reference Manual”

for more information.

PIC24FJ128GA010 Family

Secondary Oscillator

SOSCEN

Enable

Oscillator

SOSCO

SOSCI

Clock Source Option

for Other Modules

OSC2

OSC1

Primary Oscillator

XTPLL, HSPLL,

XT, HS, EC

CPU

Peripherals

CLKDIV<10:8>

WDT, PWRT

8 MHz

FRCDIV

31 kHz (Nominal)

FRC

Oscillator

LPRC

Oscillator

SOSC

LPRC

Clock Control Logic

Fail-Safe

Clock

Monitor

CLKDIV<14:12>

FRC

ECPLL, FRCPLL

CLKO

(Nominal)

4 x PLL

8 MHz/

4 MHz

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