SN75ALS056, SN75ALS057

TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS

SLLS028G – AUGUST 1987 – REVISED JUNE 1998

14

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

TEST CIRCUIT

Bus Logic

Low Level

tw is increased until the output voltage

fall just reaches 2 V.

High Level

Bus Logic

tw is increased until the output voltage rise

just reaches 0.8 V.

VOLTAGE WAVEFORMS

1.25 V

2 V

1.55 V

tw(NR)

tw(NR)

1.55 V

V1

1.85 V

1.1 V

(An, Rn)

5 V

VO

SN75ALS057

or

SN75ALS056

VI(Bn)

RL1

RL2

CL (includes jig capacitance)

NOTE A: tr = tf ≤ 5 ns from 10% to 90%

Figure 6. Receiver Noise-Immunity Test Circuit and Voltage Waveforms

TEST CIRCUIT

VOLTAGE WAVEFORMS

tPHL6

1.5 V

1.5 V

tPLH6

1.5 V

1.5 V

VO(Rn)

0

3 V

VI(Dn)

30 pF

2 V

18

Ω

(Rn)

5 V

VO

SN75ALS057

(Bn)

RL1

RL2

CL (includes jig capacitance)

VI(Dn)

NOTE A: tr = tf ≤ 5 ns from 10% to 90%

Figure 7. Driver Plus Receiver Delay-Times Test Circuits and Voltage Waveforms