M68000 datasheet(97/189 Pages) FREESCALE

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M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL

MOTOROLA

interrupt priority mask is set at level 7. In the MC68010, the VBR is forced to zero. The

vector number is internally generated to reference the reset exception vector at location 0

in the supervisor program space. Because no assumptions can be made about the validity

of register contents, in particular the SSP, neither the program counter nor the status

fetched as the initial SSP, and the address in the last two words of the reset exception

vector is fetched as the initial program counter. Finally, instruction execution is started at

the address in the program counter. The initial program counter should point to the power-

up/restart code.

The RESET instruction does not cause a reset exception; it asserts the RESET signal to

reset external devices, which allows the software to reset the system to a known state and

continue processing with the next instruction.

6.3.2 Interrupts

Seven levels of interrupt priorities are provided, numbered from 1–7. All seven levels are

available except for the 48-pin version for the MC68008.

NOTE

The MC68008 48-pin version supports only three interrupt

levels: 2, 5, and 7. Level 7 has the highest priority.

Devices can be chained externally within interrupt priority levels, allowing an unlimited

number of peripheral devices to interrupt the processor. The status register contains a 3-

bit mask indicating the current interrupt priority, and interrupts are inhibited for all priority

levels less than or equal to the current priority.

An interrupt request is made to the processor by encoding the interrupt request levels 1–7

on the three interrupt request lines; all lines negated indicates no interrupt request.

Interrupt requests arriving at the processor do not force immediate exception processing,

but the requests are made pending. Pending interrupts are detected between instruction

executions. If the priority of the pending interrupt is lower than or equal to the current

processor priority, execution continues with the next instruction, and the interrupt

exception processing is postponed until the priority of the pending interrupt becomes

greater than the current processor priority.

If the priority of the pending interrupt is greater than the current processor priority, the

exception processing sequence is started. A copy of the status register is saved; the

privilege mode is set to supervisor mode; tracing is suppressed; and the processor priority

level is set to the level of the interrupt being acknowledged. The processor fetches the

vector number from the interrupting device by executing an interrupt acknowledge cycle,

which displays the level number of the interrupt being acknowledged on the address bus.

If external logic requests an automatic vector, the processor internally generates a vector

number corresponding to the interrupt level number. If external logic indicates a bus error,

the interrupt is considered spurious, and the generated vector number references the

spurious interrupt vector. The processor then proceeds with the usual exception

processing, saving the format/offset word (MC68010 only), program counter, and status

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