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HT66F20 Datasheet(PDF) 89 Page - Holtek Semiconductor Inc |
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HT66F20 Datasheet(HTML) 89 Page - Holtek Semiconductor Inc |
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89 / 298 page  Rev. 1.90 88 �e���a�� 18� �01� Rev. 1.90 89 �e���a�� 18� �01� HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type 8-Bit MCU with EEPROM HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type 8-Bit MCU with EEPROM PGPU Register • HT66F60 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D1 D0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit7~2 Unimplemented,readas“0” Bit1~0 PGPU:PortGbit1~bit0Pull-HighControl 0:Disable 1:Enable Port A Wake-up TheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreserves power,afeaturethatisimportantforbatteryandotherlow-powerapplications.Variousmethods existtowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePort Apinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenup viaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeature usingthePAWUregister. PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D� D� D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit7~0 PAWU:PortAbit7~bit0Wake-upControl 0:Disable 1:Enable I/O Port Control Registers EachI/OporthasitsowncontrolregisterknownasPAC~PGC,tocontroltheinput/output configuration.Withthiscontrolregister,eachCMOSoutputorinputcanbereconfigured dynamicallyundersoftwarecontrol.EachpinoftheI/Oportsisdirectlymappedtoabitinits associatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthe controlregistermustbewrittenasa"1".Thiswillthenallowthelogicstateoftheinputpintobe directlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa"0", theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructions canstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfact onlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin. PAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D� D� D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 |
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