PI7C8140AMAE datasheet(13/82 Pages) PERICOM

13 / 82 page

PI7C8140A

2-PORT PCI-TO-PCI BRIDGE

Page 13 of 82

March 20, 2007 – Revision 1.01

Name

Pin Number

Type

Description

S_PAR

Secondary Parity: Parity is even across S_AD[31:0],

S_CBE#[3:0], and S_PAR (i.e. an even number of 1’s). S_PAR

is an input and is valid and stable one cycle after the address

phase (indicated by assertion of S_FRAME#) for address parity.

For write data phases, S_PAR is an input and is valid one clock

after S_IRDY# is asserted. For read data phase, S_PAR is an

output and is valid one clock after S_TRDY# is asserted. Signal

S_PAR is tri-stated one cycle after the S_AD lines are tri-stated.

During bus idle, PI7C8140A drives S_PAR to a valid logic level

when the internal grant is asserted.

S_FRAME#

STS

Secondary FRAME (Active LOW): Driven by the initiator of a

transaction to indicate the beginning and duration of an access.

The de-assertion of S_FRAME# indicates the final data phase

requested by the initiator. Before being tri-stated, it is driven to

a de-asserted state for one cycle.

S_IRDY#

STS

Secondary IRDY (Active LOW): Driven by the initiator of a

transaction to indicate its ability to complete current data phase

on the secondary side. Once asserted in a data phase, it is not de-

asserted until the end of the data phase. Before tri-stated, it is

driven to a de-asserted state for one cycle.

S_TRDY#

STS

Secondary TRDY (Active LOW): Driven by the target of a

transaction to indicate its ability to complete current data phase

on the secondary side. Once asserted in a data phase, it is not de-

asserted until the end of the data phase. Before tri-stated, it is

driven to a de-asserted state for one cycle.

S_DEVSEL#

STS

Secondary Device Select (Active LOW): Asserted by the target

indicating that the device is accepting the transaction. As a

master, PI7C8140A waits for the assertion of this signal within 5

cycles of S_FRAME# assertion; otherwise, terminate with

master abort. Before tri-stated, it is driven to a de-asserted state

for one cycle.

S_STOP#

STS

Secondary STOP (Active LOW): Asserted by the target

indicating that the target is requesting the initiator to stop the

current transaction. Before tri-stated, it is driven to a de-asserted

state for one cycle.

S_PERR#

STS

Secondary Parity Error (Active LOW): Asserted when a data

parity error is detected for data received on the secondary

interface. Before being tri-stated, it is driven to a de-asserted

state for one cycle.

S_SERR#

Secondary System Error (Active LOW): Can be driven LOW

by any device to indicate a system error condition.

S_REQ#[3:0]

99, 98, 97, 96

Secondary Request (Active LOW): This is asserted by an

external device to indicate that it wants to start a transaction on

the secondary bus. The input is externally pulled up through a

resistor to VDD.

S_GNT#[3:0]

104, 103, 101, 100

Secondary Grant (Active LOW): PI7C8140A asserts these

pins to allow external masters to access the secondary bus.

PI7C8140A de-asserts these pins for at least 2 PCI clock cycles

before asserting it again. During idle and S_GNT# deasserted,

PI7C8140A will drive S_AD, S_CBE, and S_PAR.

S_RST#

105

Secondary RESET (Active LOW): Asserted when any of the

following conditions are met:

Signal P_RESET# is asserted.

Secondary reset bit in bridge control register in

configuration space is set.

When asserted, all control signals are tri-stated and zeroes are

driven on S_AD, S_CBE, and S_PAR.

07-0067

PI7C8140AMAE Datasheet(PDF) 13 Page - Pericom Semiconductor Corporation

PI7C8140AMAE Datasheet(HTML) 13 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL