STM32F103RG datasheet(96/120 Pages) STMICROELECTRONICS

Part #	STM32F103RG

Description	XL-density performance line ARM-based 32-bit MCU with 768 KB to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces

PDF	120 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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96 / 120 page

Electrical characteristics

STM32F103xF, STM32F103xG

96/120

Doc ID 16554 Rev 3

Table 57.

I2S characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

DuCy(SCK)

I2S slave input clock duty cycle

Slave mode

fCK

1/tc(CK)

I2S clock frequency

Master mode (data: 16 bits,

Audio frequency = 48 kHz)

1.522

1.525

MHz

Slave mode

6.5

tr(CK)

tf(CK)

I2S clock rise and fall time

Capacitive load CL = 50 pF

tv(WS)

(1)

WS valid time

Master mode

th(WS)

(1)

WS hold time

Master mode

I2S2

I2S3

tsu(WS)

(1)

WS setup time

Slave mode

th(WS)

(1)

WS hold time

Slave mode

tw(CKH)

(1)

CK high and low time

Master fPCLK= 16 MHz, audio

frequency = 48 kHz

312.5

tw(CKL)

(1)

345

tsu(SD_MR)

(1)

Data input setup time

Master receiver

I2S2

I2S3

6.5

tsu(SD_SR)

(1)

Data input setup time

Slave receiver

1.5

th(SD_MR)

(1)(2)

Data input hold time

Master receiver

th(SD_SR)

(1)(2)

Slave receiver

0.5

tv(SD_ST)

(1)(2)

Data output valid time

Slave transmitter (after enable

edge)

th(SD_ST)

(1)

Data output hold time

Slave transmitter (after enable

edge)

tv(SD_MT)

(1)(2)

Data output valid time

Master transmitter (after enable

edge)

th(SD_MT)

(1)

Data output hold time

Master transmitter (after enable

edge)

Based on design simulation and/or characterization results, not tested in production.

Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.

STM32F103RG Datasheet(PDF) 96 Page - STMicroelectronics

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