2 N/C

3 GND

N/C 5

PAD

GND

Bottom View

Device

Code

N/C 2

GND 3

5 N/C

PAD

GND

Top View

B1

A1

B2

A2

V

OUT

GND

V

IN

V

EN

B1

A1

B2

A2

V

OUT

GND

V

IN

V

EN

TOP VIEW

BOTTOM VIEW

LP5900

SNVS358O – JULY 2005 – REVISED MAY 2013

www.ti.com

DESCRIPTION (CONTINUED)

The device is designed to work with 0.47

μF input and output ceramic capacitors. (No Bypass Capacitor is

required)

The device is available in DSBGA (YZR) package and WSON package. Also available in Extreme Thin SDBGA

(YPF) package. For all other package options, contact your local Texas Instruments sales office.

This device is available with 1.5V,1.575V, 1.8V, 1.9V, 2.0V, 2.1V, 2.2V, 2.3V, 2.5V, 2.6V, 2.65V, 2.7V, 2.75V

2.8V, 2.85V 3.0V, 3.3V and 4.5V outputs. Please contact your local sales office for any other voltage options.

Connection Diagrams

Figure 1. 4-Bump Thin DSBGA (YZR) Package and Extreme Thin DSBGA (YPF) Package, Large Bump

(See Package Number YZR0004/YPF0004)

Figure 2. WSON-6 Package

(See Package Number NGF0006A)

PIN DESCRIPTIONS

Pin No.

Symbol

Name and Function

DSBGA

WSON

A1

4

Enable input; disables the regulator when

≤ 0.4V. Enables the regulator when ≥

1.2V. An internal 1 M

Ω pulldown resistor connects this input to ground.

B1

3

GND

Common ground

B2

1

Output voltage. A 0.47

μF Low ESR capacitor should be connected to this Pin.

Connect this output to the load circuit.

A2

6

Input voltage supply. A 0.47 µF capacitor should be connected at this input.

2

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