FX3 datasheet(35/45 Pages) CYPRESS

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CYUSB301X

Document Number: 001-52136 Rev. *N

Page 35 of 45

I2S Timing Diagram

Figure 17. I2S Transmit Cycle

I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2 V)

fSCL

SCL clock frequency

1000

kHz

tHD:STA

Hold time START condition

0.26

–

µs

tLOW

LOW period of the SCL

0.5

–

µs

tHIGH

HIGH period of the SCL

0.26

–

µs

tSU:STA

Setup time for a repeated START condition

0.26

–

µs

tHD:DAT

Data hold time

–

µs

tSU:DAT

Data setup time

–

Rise time of both SDA and SCL signals

–

120

Fall time of both SDA and SCL signals

–

120

tSU:STO

Setup time for STOP condition

0.26

–

µs

tBUF

Bus-free time between a STOP and START condition

0.5

–

µs

tVD:DAT

Data valid time

–

0.45

µs

tVD:ACK

Data valid ACK

–

0.55

µs

tSP

Pulse width of spikes that must be suppressed by input filter

Table 13. I2C Timing Parameters[9] (continued)

Parameter

Description

Min

Max

Units

tTR

tTF

tTL

tThd

tTd

tTH

SCK

SA,

WS (output)

Table 14. I2S Timing Parameters[10]

Parameter

Description

Min

Max

Units

I2S transmitter clock cycle

Ttr

–

tTL

I2S transmitter cycle LOW period

0.35 Ttr

–

tTH

I2S transmitter cycle HIGH period

0.35 Ttr

–

tTR

I2S transmitter rise time

–

0.15 Ttr

tTF

I2S transmitter fall time

–

0.15 Ttr

tThd

I2S transmitter data hold time

–

tTd

I2S transmitter delay time

–

0.8tT

Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).

Note

10. All parameters guaranteed by design and validated through characterization.

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