AFE5809ZCF datasheet(6/90 Pages) TI

6 / 90 page

AFE5809

SLOS738C – SEPTEMBER 2012 – REVISED JANUARY 2013

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PIN FUNCTIONS (continued)

DESCRIPTION

NO.

NAME

Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be

connected between CW_IP_AMPINP and CW_IP_OUTM. This pin provides the current output for the

CW_IP_AMPINP

CW mixer. This pin becomes the CH7 PGA positive output when PGA test mode is enabled. Can be

floated if not used.

Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be

CW_IP_OUTM

connected between CW_IP_AMPINP and CW_IP_OUTPM. Can be floated if not used.

Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be

CW_IP_OUTP

connected between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used.

Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to

CW_QP_AMPIN

be connected between CW_QP_AMPINM and CW_QP_OUTP. This pin provides the current output for

the CW mixer. This pin becomes CH8 PGA negative output when PGA test mode is enabled. Can be

floated if not used.

Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be

connected between CW_QP_AMPINP and CW_QP_OUTM. This pin provides the current output for

CW_QP_AMPINP

the CW mixer. This pin becomes CH8 PGA positive output when PGA test mode is enabled. Can be

floated if not used.

Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to

CW_QP_OUTM

be connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used.

Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor has to

CW_QP_OUTP

be connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used.

N8, P9~P7, P3

D1M to D8M

ADC CH1 to 8 LVDS negative outputs

to P1, N2

N9, R9~R7,

D1P to D8P

ADC CH1 to 8 LVDS positive outputs

R3 to R1, N1

DCLKM

LVDS bit clock (7x) negative output

DCLKP

LVDS bit clock (7x) positive output

N3, N7

DVDD

ADC digital and I/O power supply, 1.8 V

N5, P5, R5

DVSS

ADC digital ground

DVDD_LDO1,

Demodulator digital power supply generated internally. These two pins should be separated on PCB

N4, N6

DVDD_LDO2

and decoupled respectively with 0.1µF capacitors.

FCLKM

LVDS frame clock (1X) negative output

FCLKP

LVDS frame clock (1X) positive output

CH1 to 8 complimentary analog inputs. Bypass to ground with

≥ 0.015µF capacitors. The HPF

C9 to C2

INM1…INM8

response of the LNA depends on the capacitors.

A9 to A2

INP1...INP8

CH1to 8 analog inputs. AC couple to inputs with

≥ 0.1µF capacitors.

LDO_EN

Must be tied to 1.8 V DVDD.

LDO_SETV

Must be tied to 1.8 V DVDD.

ADC partial (fast) power down control pin with an internal pull down resistor of 100 k

Ω. Active High.

PDN_ADC

Either 1.8 V or 3.3 logic level can be used.

VCA partial (fast) power down control pin with an internal pull down resistor of 20 k

Ω. Active High. 3.3

PDN_VCA

V logic level should be used.

Global (complete) power-down control pin for the entire chip with an internal pull down resistor of 20

PDN_GLOBAL

Ω. Active High. 3.3 V logic level should be used.

0.5 V reference output in the internal reference mode. Must leave floated in the internal reference

REFM

mode. Adding a test point on the PCB is recommended for monitoring the reference output

1.5 V reference output in the internal reference mode. Must leave floated in the internal reference

REFP

mode. Adding a test point on the PCB is recommended for monitoring the reference output

Hardware reset pin with an internal pull-down resistor of 20 k

Ω. Active high. 3.3 logic level can be

RESET

used.

Serial interface clock input with an internal pull-down resistor of 20 k

Ω. This pin is connected to both

SCLK

ADC and VCA. 3.3 V logic should be used.

Serial interface data input with an internal pull-down resistor of 20 k

Ω. This pin is connected to both

SDATA

ADC and VCA. 3.3 V logic should be used.

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