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ICS954201BGLF Datasheet(PDF) 12 Page - Integrated Device Technology

Part # ICS954201BGLF
Description  Programmable Timing Control Hub??for Mobile P4??Systems
PDF  16 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS954201BGLF Datasheet(HTML) 12 Page - Integrated Device Technology

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ICS954201
0819H—02/17/06
SMBus Table: SRC Stop Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRCCLK7
RW
Free-Running
Stoppable
0
Bit 6
SRCCLK6
RW
Free-Running
Stoppable
0
Bit 5
SRCCLK5
RW
Free-Running
Stoppable
0
Bit 4
SRCCLK4
RW
Free-Running
Stoppable
0
Bit 3
SRCCLK3
RW
Free-Running
Stoppable
0
Bit 2
SRCCLK2
RW
Free-Running
Stoppable
0
Bit 1
SRCCLK1
RW
Free-Running
Stoppable
0
Bit 0
SRCCLK0
RW
Free-Running
Stoppable
0
SMBus Table: Stop and Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
X
Bit 6
DOT_96MHz
Driven in PD
RW
Driven
Hi-Z
0
Bit 5
0
Bit 4
PCI_F1
RW
Free-Running
Stoppable
0
Bit 3
PCI_F0
RW
Free-Running
Stoppable
0
Bit 2
CPUCLK2_ITP
RW
Free-Running
Stoppable
1
Bit 1
CPUCLK1
RW
Free-Running
Stoppable
1
Bit 0
CPUCLK0
RW
Free-Running
Stoppable
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC_STOP Drive Mode
Driven in
PCI/SRC_STOP#
RW
Driven
Hi-Z
0
Bit 6
CPUCLK2_ITP_STOP Drive Mode
RW
Driven
Hi-Z
0
Bit 5
CPUCLK1_STOP Drive Mode
RW
Driven
Hi-Z
0
Bit 4
CPUCLK0_STOP Drive Mode
RW
Driven
Hi-Z
0
Bit 3
SRC_PD Drive Mode
RW
Driven
Hi-Z
0
Bit 2
CPUCLK2_ITP_PD Drive Mode
RW
Driven
Hi-Z
0
Bit 1
CPUCLK1_PD Drive Mode
RW
Driven
Hi-Z
0
Bit 0
CPUCLK0_PDDrive Mode
RW
Driven
Hi-Z
0
Driven in CPU_STOP#
Driven in Powerdown
(PD)
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
PCICLK_F outputs
RESERVED
Allow assertion of
CPU_STOP# to stop
CPUCLK outputs
RESERVED
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
SRC clocks
41,40
44,43
44,43
SRCCLK(7:0)
36,35
44,43
9
31,30
26,27
8
36,35
41,40
24,25
22,23
19,20
Byte 4
17,18
Byte 3
36,35
33,32
Byte 5
SRCCLK(7:0)
36,35
41,40
14,15



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