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STM8S003K3 Datasheet(PDF) 66 Page - STMicroelectronics |
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STM8S003K3 Datasheet(HTML) 66 Page - STMicroelectronics |
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66 / 100 page ![]() (1) Data based on characterization results, not tested in production. (2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. I/O port pin characteristics 9.3.6 General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 37: I/O static characteristics Unit Max Typ Min Conditions Parameter Symbol V 0.3 x VDD -0.3 V VDD = 5 V Input low level voltage VIL VDD + 0.3 0.7 x VDD Input high level voltage VIH mV 700 Hysteresis (1) Vhys kΩ 80 55 30 VDD = 5 V, VIN = VSS Pull-up resistor Rpu ns 20 (2) Fast I/Os Load = 50 pF Rise and fall time (10 % - 90 %) tR, tF 125 (2) Standard and high sink I/Os Load = 50 pF μA ±1 (2) VSS ≤ VIN ≤VDD Digital input leakage current Ilkg nA ±250 (2) VSS ≤ VIN ≤ VDD Analog input leakage current Ilkg ana μA ±1 (2) Injection current ±4 mA Leakage current in adjacent I/O Ilkg(inj) (1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. (2)Data based on characterisation results, not tested in production. DocID018576 Rev 3 66/100 STM8S003K3 STM8S003F3 Electrical characteristics |
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