AD7091R datasheet(13/20 Pages) AD

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Data Sheet

AD7091R

Rev. 0 | Page 13 of 20

TYPICAL CONNECTION DIAGRAM

Figure 22 shows a typical connection diagram for the AD7091R.

A positive power supply in the range of 2.7 V to 5.25 V should

be connected to the VDD pin, with typical values for decoupling

capacitors being 100 nF and 10 µF. These capacitors should be

placed as close as possible to the device pins. With the power

supply connected to the VDD pin, the AD7091R operates with

the internal 2.5 V reference, and the REFIN/REFOUT pin should

be decoupled using a capacitor with a typical value of 2.2 µF to

achieve the specified performance and provide an analog input

range of 0 V to VREF. The typical value for the regulator bypass

decoupling capacitor (REGCAP) is 1 µF. The voltage applied to

the VDRIVE input controls the voltage of the serial interface;

therefore, this pin should be connected to the supply voltage of

the microprocessor. VDRIVE can be set in the range of 1.65 V to

5.25 V. Typical values for the VDRIVE decoupling capacitors are

100 nF and 10 µF. The conversion result is output in a 12-bit

word with the MSB first.

The AD7091R requires the user to initiate a software reset upon

power-up (see the Software Reset section).

If an external reference is applied to the device, the internal

reference is automatically overdriven. An externally applied

reference voltage should be in the range of 2.7 V to 5.25 V and

should be connected to the REFIN/REFOUT pin.

If the BUSY indicator feature is required, a pull-up resistor of

typically 100 kΩ to VDRIVE should be connected to the SDO pin.

In addition, for applications in which power consumption is a

concern, the power-down mode can be used to improve the

power performance of the ADC (see the Modes of Operation

section for more details).

ANALOG INPUT

Figure 21 shows an equivalent circuit of the AD7091R analog

input structure. The D1 and D2 diodes provide ESD protection

for the analog input. The D3 diode is a parasitic diode between

VIN and VREF. To prevent the diodes from becoming forward-

biased and from starting to conduct current, ensure that the

analog input signal never exceeds VREF or VDD by more than

300 mV. These diodes can conduct a maximum of 10 mA

without causing irreversible damage to the part.

Figure 21. Equivalent Analog Input Circuit

Capacitor C1 in Figure 21 is typically about 1 pF and can

primarily be attributed to pin capacitance. Resistor R1 is a

lumped component made up of the on resistance of a switch.

This resistor is typically about 500 Ω. Capacitor C2 is the ADC

sampling capacitor and typically has a capacitance of 3.6 pF.

In applications where harmonic distortion and signal-to-noise

ratio are critical, the analog input should be driven from a low

impedance source. Large source impedances significantly affect

the ac performance of the ADC. This may necessitate using an

input buffer amplifier as shown in Figure 22. The choice of the

op amp is a function of a particular application.

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum source

impedance depends on the amount of total harmonic distortion

(THD) that can be tolerated. The THD increases as the source

impedance increases and performance degrades. Figure 10 shows a

graph of THD vs. source impedance when using a supply voltage

of 3 V and a sampling rate of 1 MSPS.

Use an external filter—such as a one-pole, low-pass RC filter, or

similar, as shown in Figure 22—on the analog input connected

to the AD7091R to achieve the specified performances.

Figure 22. AD7091R Typical Connection Diagram

3.6pF

VDD

VIN

1pF

2.5pF

NOTES

1. DURING THE CONVERSION PHASE, THE SWITCH IS OPEN.

DURING THE TRACK PHASE, THE SWITCH IS CLOSED.

VREF

AD7091R

SCLK

SDO

MICROPROCESSOR/

MICROCONTROLLER/

DSP

VIN

GND

VDD

10µF

100nF

10µF

100nF

REGCAP

1µF

CONVST

2.2µF

ANALOG

INPUT

51Ω

4.7nF

100kΩ

WITH BUSY

INDICATION

VDRIVE

2.7V TO 5.25V

1.65V TO 5.25V

VDRIVE

REFIN/

REFOUT

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