IRSM836-024MA

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© 2013 International Rectifier

February 3, 2013

PCB Example

Figure 7 below shows an example layout for the application PCB. The effective area of the V+ top-layer

can be achieved using thicker copper and/or additional layers.

Figure 7: PCB layout example and corresponding thermal image (6kHz, 2P, 2oz,

∆Tca=40°C, V+ = 150V, Iu = 427mArms, Po

= 94W)

At the module’s typical operating conditions, dV/dt of the phase node voltage is influenced by the load

capacitance which includes parasitic capacitance of the PCB, MOSFET output capacitance and motor winding

capacitance. To turn off the MOSFET, the load capacitance needs to be charged by the phase current. For the

IRMCS1171 reference design, turn-off dV/dt ranges from 2 to 5 V/ns depending on the phase current magnitude.

Turn-on dV/dt is influenced by PCB parasitic capacitance and motor winding capacitance and typically ranges

from 4 to 6 V/ns. The MOSFET turn-on loss combined with the complimentary body diode reverse recovery loss

comprises the majority of the total switching losses. Two-phase modulation can be used to reduce switching

losses and run the module at higher phase currents.

Module