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DSPIC33FJ12MC201TESS Datasheet(PDF) 152 Page - Microchip Technology

Part # DSPIC33FJ12MC201TESS
Description  High-Performance, 16-bit Digital Signal Controllers
PDF  304 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC33FJ12MC201TESS Datasheet(HTML) 152 Page - Microchip Technology

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dsPIC33FJ12MC201/202
DS70265E-page 152
© 2007-2011 Microchip Technology Inc.
14.1
Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 14-1 lists the different bit settings for the Output
Compare modes. Figure 14-2 illustrates the output
compare operation for various modes. The user
application must disable the associated timer when
writing to the output compare control registers to avoid
malfunctions.
TABLE 14-1:
OUTPUT COMPARE MODES
Note:
See Section 13. “Output Compare” in
the “dsPIC33F/PIC24H Family Reference
Manual”
(DS70209) for OCxR and
OCxRS register restrictions.
OCM<2:0>
Mode
OCx Pin Initial State
OCx Interrupt Generation
000
Module Disabled
Controlled by GPIO register
—
001
Active-Low One-Shot
0
OCx Rising edge
010
Active-High One-Shot
1
OCx Falling edge
011
Toggle Mode
Current output is maintained
OCx Rising and Falling edge
100
Delayed One-Shot
0
OCx Falling edge
101
Continuous Pulse mode
0
OCx Falling edge
110
PWM mode without fault
protection
0
, if OCxR is zero
1
, if OCxR is non-zero
No interrupt
111
PWM mode with fault protection 0, if OCxR is zero
1
, if OCxR is non-zero
OCFA Falling edge for OC1 to OC4



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