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STM8AF6146 Datasheet(PDF) 65 Page - STMicroelectronics |
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STM8AF6146 Datasheet(HTML) 65 Page - STMicroelectronics |
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65 / 89 page ![]() STM8AF61xx, STM8AF62xx Electrical characteristics Doc ID 14952 Rev 6 65/89 10.3.8 TIM 1, 2, 3, and 4 timer specifications Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified. 10.3.9 SPI serial peripheral interface Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 39. TIM 1, 2, 3, and 4 electrical specifications Symbol Parameter Conditions Min Typ Max Unit fEXT Timer external clock frequency(1) 1. Not tested in production. On 64 Kbyte devices, the frequency is limited to 16 MHz. -- - 16 MHz Table 40. SPI characteristics Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode 0 10 MHz Slave mode VDD < 4.5 V 0 6(1) VDD = 4.5 V to 5.5 V 0 8(1) tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF - 25(2) ns tsu(NSS) (3) NSS setup time Slave mode 4 * tMASTER - th(NSS) (3) NSS hold time Slave mode 70 - tw(SCKH) (3) tw(SCKL) (3) SCK high and low time Master mode tSCK/2 - 15 tSCK/2 + 15 tsu(MI) (3) tsu(SI) (3) Data input setup time Master mode 5 - Slave mode 5 - th(MI) (3) th(SI) (3) Data input hold time Master mode 7 - Slave mode 10 - ta(SO) (3)(4) Data output access time Slave mode - 3* tMASTER tdis(SO) (3)(5) Data output disable time Slave mode 25 tv(SO) (3) Data output valid time Slave mode (after enable edge) VDD < 4.5 V - 75 VDD = 4.5 V to 5.5 V - 53 tv(MO) (3) Data output valid time Master mode (after enable edge) - 30 th(SO) (3) Data output hold time Slave mode (after enable edge) 31 - th(MO) (3) Master mode (after enable edge) 12 - 1. fSCK < fMASTER/2. 2. The pad has to be configured accordingly (fast mode). 3. Values based on design simulation and/or characterization results, and not tested in production. |
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