STM32F101RBH6 datasheet(55/90 Pages) STMICROELECTRONICS

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STM32F101x8, STM32F101xB

Electrical characteristics

5.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 34 are derived from tests

performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL

compliant.

Table 34. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Low level input

voltage

Standard IO

input low level

voltage

0.28*(VDD-2 V)+0.8 V(1)

IO FT(3) input low

level voltage

0.32*(VDD-2 V)+0.75 V(1)

All I/Os except

BOOT0

0.35VDD(2)

VIH

High level input

voltage

Standard IO

input high level

voltage

0.41*(VDD-2 V)+1.3

V(1)

IO FT(3) input

high level voltage

0.42*(VDD-2 V)+1 V(1)

All I/Os except

BOOT0

0.65VDD(2)

Vhys

Standard IO Schmitt

trigger voltage

hysteresis(4)

200

IO FT Schmitt trigger

voltage hysteresis(4)

5% VDD(5)

Ilkg

Input leakage current

(6)

VSS  VIN VDD

Standard I/Os

1

µA

VIN = 5 V

I/O FT

RPU

Weak pull-up

equivalent resistor(7)

VIN VSS



RPD

Weak pull-down

equivalent resistor(7)

VIN VDD

CIO

I/O pin capacitance

1. Data based on design simulation.

2. Tested in production.

3. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be

disabled.

4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

5. With a minimum of 100 mV.

6. Leakage could be higher than max. if negative current is injected on adjacent pins.

7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order)

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