EP2C8 datasheet(14/36 Pages) ALTERA

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Page 14

Functional Description

Enhanced Configuration (EPC) Devices Datasheet

January 2012

Altera Corporation

The EPC device controller chip accesses flash memory during:

■

FPGA configuration—reading configuration data from flash

■

JTAG-based flash programming—storing configuration data in flash

■

At POR—reading option bits from flash

During these operations, the external FPGA or processor must tri-state its interface to

the flash memory. After configuration and programming, the EPC device’s controller

tri-states the internal interface and goes into an idle mode. To interrupt a

configuration cycle in order to access the flash using the external flash interface, the

external device can hold the FPGA’s nCONFIG input low. This keeps the configuration

device in reset by holding the nSTATUS-OE line low, allowing external flash access.

f For more information about the software support for the external flash interface

feature, refer to the Altera Enhanced Configuration Devices.

EP2C8 Datasheet(PDF) 14 Page - Altera Corporation