TMP411

SBOS383C − DECEMBER 2006 − REVISED MAY 2008

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17

TIMING DIAGRAMS

The TMP411 is Two-Wire and SMBus-compatible.

Figure 13 to Figure 17 describe the various operations on

the TMP411. Bus definitions are given below. Parameters

for Figure 13 are defined in Table 12.

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line,

from high to low, while the SCL line is high, defines a

START condition. Each data transfer is initiated with a

START condition.

Stop Data Transfer: A change in the state of the SDA line

from low to high while the SCL line is high defines a STOP

condition. Each data transfer terminates with a STOP or a

repeated START condition.

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not limited and

is determined by the master device. The receiver

acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed,

is obliged to generate an Acknowledge bit. A device that

acknowledges must pull down the SDA line during the

Acknowledge clock pulse in such a way that the SDA line

is stable low during the high period of the Acknowledge

clock pulse. Setup and hold times must be taken into

account. On a master receive, data transfer termination

can

be

signaled

by

the

master

generating

a

Not-Acknowledge on the last byte that has been

transmitted by the slave.

SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(B U F)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

PS

SP

Figure 13. Two-Wire Timing Diagram

Table 12. Timing Diagram Definitions for Figure 13

PARAMETER

FAST MODE

HIGH-SPEED MODE

UNITS

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCL Operating Frequency

f(SCL)

0.001

0.4

0.001

3.4

MHz

Bus Free Time Between STOP and START Condition

t(BUF)

600

160

ns

Hold time after repeated START condition.

After this period, the first clock is generated.

t(HDSTA)

100

100

ns

Repeated START Condition Setup Time

t(SUSTA)

100

100

ns

STOP Condition Setup Time

t(SUSTO)

100

100

ns

Data Hold Time

t(HDDAT)

0(1)

0(2)

ns

Data Setup Time

t(SUDAT)

100

10

ns

SCL Clock LOW Period

t(LOW)

1300

160

ns

SCL Clock HIGH Period

t(HIGH)

600

60

ns

Clock/Data Fall Time

tF

300

160

ns

Clock/Data Rise Time

tR

300

160

ns

for SCLK

≤ 100kHz

tR

1000

ns

(1) For cases with fall time of SCL less than 20ns and/or the rise time or fall time of SDA less than 20ns, the hold time should be greater than 20ns.

(2) For cases with fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than 10ns.