(

)

2

OUT

LOAD(max)

OUT(min_ over)

LOAD(release)

OUT

L

I

C

2

V

V

´ D

=

´ D

´

(

OUT

SW

LOAD(max)

MIN(off )

IN(min)

OUT(min_ under)

IN(min)

OUT

LOAD(insert)

SW

MIN(off )

OUT

IN(min)

V

t

L

I

t

V

C

V

V

2

V

t

t

V

V

æ

ö

´

´ D

´

+

ç

÷

ç

÷

è

ø

=

æ

ö

æ

ö

-

ç

÷

´ D

´

´

-

´

ç

÷

ç

÷

ç

÷

è

ø

è

ø

SW

0

f

f

200 kHz

4

=

=

TPS51363

SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013

www.ti.com

Stability considerations

The switching frequency of the design example is 800 kHz (which is set by the MODE pin, see Table 4). For D-

CAP2 mode operation, it is generally recommended to have a unity gain crossover (f0) of less than 1/4 or 1/3 of

the switching frequency, which is approximately between 200 kHz and 266 kHz. In this design example, use 1/4.

(7)

Given the range of the recommended unity gain crossover frequency, the power stage design is flexible, as long

When the above criterion is met, the internal compensation network provides sufficient phase boost at the unity

gain crossover frequency such that the converter is stable with sufficient phase margin (greater than 60°).

When the ESR frequency of the output bulk capacitor is in the vicinity of the unity gain crossover frequency of

the loop, additional phase boost can be achieved. This applies to higher ESR output bulk capacitor, POSCAP

and SPCAP.

When the ESR frequency of the output capacitor is beyond the unity gain crossover frequency of the control

loop, no additional phase boost is achieved. This applies to low or ultra low ESR output capacitor, such as

MLCCs.

For this application example,consider only all MLCCs for output capacitors. Based on Equation 3 and Equation 7,

the minimum capacitance for stable operation is calculated to be 110 µF.

Transient considerations

•

•

di/dt = 2.5 A/µs

•

Use Equation 8 and Equation 9 to estimate the amount of capacitance needed for a given dynamic load/release.

(8)

(9)

Based on these calculation, to meet the transient requirement, the minimum amount of capacitance in this design

is 164 µF.

Considering both stability and transient, the minimum capacitance is 164 µF. The design example uses 8, 22-µF

capacitors with minor consideration of the MLCC derating for both DC and AC effect.

Step Eight: Select decoupling and peripheral components

For the TPS51363, peripheral capacitors use the following minimum values of ceramic capacitance. X5R or

better temperature coefficient is recommended. Tighter tolerance and higher voltage rating are always

appropriate.

•

V5IN decoupling

≥ 2.2 µF, ≥ 10 V

•

VREF decoupling 0.1 µF to 1 µF,

≥ 4 V

•

Bootstrap capacitor

≥ 0.1 µF, ≥ 10 V

•

Pull-up resistors on PGOOD, 100 k

Ω

Step Nine: Layout guidelines

Figure 31 applies to the layer where device is situated. Additional reinforcement of VIN, PGND, and VOUT

through vias are always recommended.

20

Submit Documentation Feedback

Copyright © 2013, Texas Instruments Incorporated

Product Folder Links: TPS51363