Micrel, Inc.

MAQRF112

February 7, 2013

2

Revision 1.0

Pin Configuration

10-Pin MSOP (YMM)

Pin Description

Pin Number

Pin Name

Pin Function

1

ASK

ASK Data Input and PA Enable. When EN is set to a logic-level HIGH and ASK is set to a logic-

level HIGH, the power amplifier (PA) is enabled. A logic-level LOW on ASK disables the power

amplifier. Apply a data stream less than 50Kbps (Manchester Encoded, 50% duty-cycle) for ASK

modulation. To transmit with FSK modulation, both EN and ASK need to be set to a logic-level

HIGH, while the FSK pin is modulated.

2

XTLIN

Reference Oscillator Input Connection. Connect a crystal between XTLIN and XTLOUT. Connect

a load capacitor from XTLIN to ground, based on the recommendations of the crystal

manufacturer.

3

XTLOUT

Reference Oscillator Output Connection. Connect a crystal between XTLIN and XTLOUT.

Connect a load capacitor from XTLOUT to ground, based on the recommendations of the crystal

manufacturer.

4

VSS

Ground.

5

XTAL_MOD

FSK Crystal Pulling Switch Connection. For FSK modulation, connect a capacitor between the

XTAL_MOD pin and XTLOUT. For ASK-only operation, this pin can be left unconnected.

6

FSK

FSK Data Input. A logic-level LOW opens the FSK crystal pulling switch, providing high

impedance (>1M

Ω) between the XTAL_MOD pin and VSS (ground). A logic-level HIGH closes

the switch, providing low impedance (15

Ω) between XTAL_MOD and VSS (ground). This parallels

frequency to achieve FSK modulation. For ASK-only operation, pulling this pin low is

recommended.

7

EN

Enable/Shutdown Input. A logic-level LOW disables the entire device, placing it in a low-power

shutdown mode. A logic-level HIGH enables the crystal oscillator, PLL, voltage-controlled

oscillator (VCO), and control blocks, if the supply voltage is above the undervoltage lockout

(UVLO) voltage. The power amplifier is enabled when a logic-level HIGH is applied to EN and

ASK.

8

VSSPA

Power Amplifier Ground.

9

PAOUT

Open Collector of Power Amplifier Output. Pull the PA_OUT pin to VDD through an inductor to

properly bias the output stage. Add a pull-up resistor in series to reduce bias current and to

achieve lower output power and lower supply current operation. A matching network is required to

match the output to desired load (PCB antenna, wire antenna, or 50

Ω load) to achieve best output

power, supply current, and spectral performance. See the “Applications Information” section for

recommended power supply bypassing.

10

VDD

Power Supply for Crystal Oscillator, Phase-Locked Loop, Voltage-Controlled Oscillator, and

Control Blocks. See the “Applications Information” section for recommended power supply

bypassing.