Arizona Microtek, Inc.

AZP53

Low Phase Noise Sine Wave/CMOS

to LVPECL Buffer/Translator

www.azmicrotek.com

+1-480-962-5881

7

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Mar 2013, Rev 2.2

Arizona Microtek’s evaluation board EBP53 provides the most convenient way to test and prototype AZP53 series

circuits. Built for the AZP53Q 1.5x1.0 mm package, it is designed to support both dual and single supply operation. Dual

M1

M2

M3

M4

D

M5

21.1mA

21.1mA

16mA

Q

Q

50

Ω

50

Ω

21.1mA - High

5.1mA - Low

Test

Equipment

Terminations

Output

Stage

Figure 7 - Split Supply LVPECL Output Termination

Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 8 below

shows the AC coupling technique. The 200

Ω resistors form the required DC loads, and the 50Ω resistors provide the AC

termination. The parallel combination of the 200

Ω and 50Ω resistors results in a net 40Ω AC load termination. In many

cases this will work well. If necessary, the 50

Ω resistors can be increased to about 56Ω. Alternately, bias tees combined

with current setting resistors will eliminate the lowered AC load impedance. The 50

Ω resistors are typically connected to

ground but can be connected to the bias level needed by the succeeding stage.