MCP79400 datasheet(19/42 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

DS25009C-page 19

MCP7940X

6.0

ON BOARD MEMORY

The MCP7940X has both on-board Unique ID memory

and battery-backed SRAM. The SRAM is arranged as

64 x 8 bytes and is retained when the VCC supply is

removed, provided the VBAT supply is present and

enabled. The Unique ID is nonvolatile memory and

does not require the VBAT supply for retention.

6.1

SRAM

FIGURE 6-1:

SRAM/RTCC BYTE WRITE

FIGURE 6-2:

SRAM/RTCC MULTIPLE BYTE WRITE

The 64 bytes of user SRAM are at location 0x20h and

can be accessed during an RTCC update. Upon POR

the SRAM will be in an undefined state.

Writing to the SRAM and RTCC is accomplished in a

similar way to writing to the EEPROM (as described

later in this document) with the following consider-

ations:

• There is no page. The entire 64 bytes of SRAM or

32 bytes of RTCC register can be written in one

command.

• The SRAM allows an unlimited number of read/

write cycles with no cell wear out.

• The RTCC and SRAM are not accessible when

the device is running on the external VBAT.

• The RTCC and SRAM are separate blocks. The

SRAM array may be accessed during an RTCC

update.

• Read and write access is limited to either the

RTCC register block or the SRAM array. The

Address Pointer will rollover to the start of the

addressed block.

• Data written to the RTCC and SRAM are on a per

byte basis.

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

ADDRESS

BYTE

DATA

S 110 1

1 11

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

ADDRESS

BYTE

DATA BYTE 0

DATA BYTE N

S 1 101

111

Note:

Entering an address past 5F for an SRAM

operation will result in the MCP7940X not

acknowledging the address.

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