PIC24FJ64GA108 datasheet(6/22 Pages) MICROCHIP

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PIC24FJ256GA110 FAMILY

DS80368N-page 6

 2008-2013 Microchip Technology Inc.

8. Module: UART (UxERIF Interrupt)

The UART error interrupt may not occur, or occur

at an incorrect time, if multiple errors occur during

a short period of time.

Work around

Read the error flags in the UxSTA register when-

ever a byte is received to verify the error status. In

most cases, these bits will be correct, even if the

UART error interrupt fails to occur. For possible

exceptions, refer to Errata # 9.

Affected Silicon Revisions

9. Module: UART (FIFO Error Flags)

Under certain circumstances, the PERR and

FERR error bits may not be correct for all bytes in

the receive FIFO. This has only been observed

when both of the following conditions are met:

• the UART receive interrupt is set to occur when

the FIFO is full or ¾ full



(UxSTA<7:6> = 1x), and

• more than 2 bytes with an error are received.

In these cases, only the first two bytes with a parity

or framing error will have the corresponding bits

indicate correctly. The error bits will not be set after

this.

Work around

None.

Affected Silicon Revisions

10. Module: SPIx (Enhanced Buffer Modes)

If the SPIx event interrupt is configured to occur

when

the

enhanced

FIFO

buffer

full

(SISEL<2:0> = 111), the interrupt may actually

occur when the 7th byte is written to the buffer,

instead of the 8th byte. The other enhanced buffer

interrupts function as previously described.

Work around

Do not use the Full Buffer Interrupt mode. The

SPITBF bit (SPIxSTAT<1>) reliably indicates when

the enhanced FIFO buffer is full, and can be polled

instead of using the Full Buffer Interrupt mode.

Affected Silicon Revisions

11. Module: UART (IrDA®)

When the UART is operating in 8-bit mode

(PDSEL<1:0> = 0x) and using the IrDA endec

(IREN = 1), the module incorrectly transmits a

data payload of 80h as 00h.

Work around:

None.

Affected Silicon Revisions

12. Module: UART (IrDA)

When the UART is operating in 8-bit mode

(PDSEL<1:0> = 0x) and using the IrDA endec

(IREN = 1), a framing error may occur when

transmitting a data payload of 00h.

Work around:

None.

Affected Silicon Revisions

13. Module: UART (IrDA)

When the UART is operating in 9-bit mode

(PDSEL<1:0> = 1x) and using the IrDA endec

(IREN = 1), the module will incorrectly transmit

10 bits when transmitting data payloads of 00h or

80h.

Work around:

None.

Affected Silicon Revisions

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