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ADSP-21486KSWZ-2AB Datasheet(PDF) 50 Page - Analog Devices |
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ADSP-21486KSWZ-2AB Datasheet(HTML) 50 Page - Analog Devices |
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50 / 68 page  Rev. B | Page 50 of 68 | March 2013 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 SPI Interface—Slave Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Min Max Unit Timing Requirements tSPICLKS Serial Clock Cycle 4 × tPCLK – 2 ns tSPICHS Serial Clock High Period 2 × tPCLK – 2 ns tSPICLS Serial Clock Low Period 2 × tPCLK – 2 ns tSDSCO SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 2 × tPCLK ns tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × tPCLK ns tSSPIDS Data Input Valid to SPICLK edge (Data Input Set-up Time) 2 ns tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid 2 ns tSDPPW SPIDS Deassertion Pulse Width (CPHASE=0) 2 × tPCLK ns Switching Characteristics tDSOE SPIDS Assertion to Data Out Active 0 7.5 ns tDSOE 1 SPIDS Assertion to Data Out Active (SPI2) 0 7.5 ns tDSDHI SPIDS Deassertion to Data High Impedance 0 10.5 ns tDSDHI 1 SPIDS Deassertion to Data High Impedance (SPI2) 0 10.5 ns tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 ns tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × tPCLK ns tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × tPCLK ns 1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral Interface Port” chapter. Figure 36. SPI Slave Timing tSPICHS tSPICLS tSPICLKS tHDS tSDPPW tSDSCO tDSOE tDDSPIDS tDDSPIDS tDSDHI tHDSPIDS tHSPIDS tSSPIDS tDSDHI tDSOV tHSPIDS tHDSPIDS SPIDS (INPUT) MISO (OUTPUT) MOSI (INPUT) MISO (OUTPUT) MOSI (INPUT) CPHASE = 1 CPHASE = 0 SPICLK (CP = 0, CP = 1) (INPUT) tSSPIDS |
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