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PIC12F510I/MS Datasheet(PDF) 20 Page - Microchip Technology |
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PIC12F510I/MS Datasheet(HTML) 20 Page - Microchip Technology |
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20 / 124 page  PIC12F510/16F506 DS41268D-page 18 © 2007 Microchip Technology Inc. TABLE 4-2: SPECIAL FUNCTION REGISTER SUMMARY – PIC16F506 4.3 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS regis- ter. These instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section 11.0 “Instruction Set Summary”. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset N/A TRIS I/O Control Registers (TRISB, TRISC) --11 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx 02h(1) PCL Low Order 8 bits of PC 1111 1111 03h STATUS RBWUF CWUF PA0 TO PD ZDC C 0001 1xxx 04h FSR Indirect Data Memory Address Pointer 100x xxxx 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 08h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 09h ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON 1111 1100 0Ah ADRES ADC Conversion Result xxxx xxxx 0Bh CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 0Ch VRCON VREN VROE VRR —(2) VR3 VR2 VR1 VR0 0011 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to access these bits. 2: Unimplemented bit VRCON<4> read as ‘1’. |
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