DESCRIPTION CONTINUED

CDCVF2510A

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

The CDCVF2510A is characterized for operation from 0°C to 85°C.

For application information see the application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL With Spread

Spectrum Clocking (SSC) (literature number SCAA039).

FUNCTION TABLE

INPUTS

OUTPUTS

PLL

AVDD

G

CLK

1Y(0:9)

FBOUT

GND

L

Signal

L

Signal (delayed)

Bypassed / Off

GND

H

Signal

Signal (delayed)

Signal (delayed)

Bypassed / Off

3.3 V (nom)

L

CLK > 1 MHz

L

CLK (in phase)

On

3.3 V (nom)

H

CLK > 1 MHz

CLK (in phase)

CLK (in phase)

On

3.3 V (nom)

X

CLK < 1 MHz

L

L

Off

2

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