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DS90C032TMX/NOPB Datasheet(PDF) 5 Page - Texas Instruments

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Part # DS90C032TMX/NOPB
Description  DS90C032 LVDS Quad CMOS Differential Line Receiver
PDF  18 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DS90C032TMX/NOPB Datasheet(HTML) 5 Page - Texas Instruments

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DS90C032
www.ti.com
SNLS094D – JUNE 1998 – REVISED APRIL 2013
Switching Characteristics
VCC = +5.0V ± 10%, TA = −40°C to +85°C, DS90C032T
(1) (2) (3) (4) (5)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHLD
Differential Propagation Delay High to Low
CL = 5 pF,
1.0
3.40
6.0
ns
VID = 200 mV,
tPLHD
Differential Propagation Delay Low to High
1.0
3.48
6.0
ns
See Figure 2 and Figure 3
tSKD
Differential Skew |tPHLD − tPLHD|
0
0.08
1.2
ns
tSK1
Channel-to-Channel Skew (3)
0
0.6
1.5
ns
tSK2
Chip to Chip Skew (4)
5.0
ns
tTLH
Rise Time
0.5
2.5
ns
tTHL
Fall Time
0.5
2.5
ns
tPHZ
Disable Time High to Z
RL = 2 kΩ,
10
20
ns
CL = 10 pF,
tPLZ
Disable Time Low to Z
10
20
ns
See Figure 4 and Figure 5
tPZH
Enable Time Z to High
4
15
ns
tPZL
Enable Time Z to Low
4
15
ns
(1)
All typical values are given for: VCC = +5.0V, TA = +25°C.
(2)
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns
for EN or EN*.
(3)
Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
(4)
Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
(5)
CL includes probe and jig capacitance.
Switching Characteristics
VCC = +5.0V ± 10%, TA = −55°C to +125°C, DS90C032E
(1) (2) (3) (4) (5) (6)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHLD
Differential Propagation Delay High to Low
CL = 20 pF,
1.0
3.40
8.0
ns
VID = 200 mV,
tPLHD
Differential Propagation Delay Low to High
1.0
3.48
8.0
ns
See Figure 2 and Figure 3
tSKD
Differential Skew |tPHLD − tPLHD|
0
0.08
3.0
ns
tSK1
Channel-to-Channel Skew (3)
0
0.6
3.0
ns
tSK2
Chip to Chip Skew (4)
7.0
ns
tPHZ
Disable Time High to Z
RL = 2 kΩ,
10
20
ns
CL = 10 pF,
tPLZ
Disable Time Low to Z
10
20
ns
See Figure 4 and Figure 5
tPZH
Enable Time Z to High
4
20
ns
tPZL
Enable Time Z to Low
4
20
ns
(1)
All typical values are given for: VCC = +5.0V, TA = +25°C.
(2)
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns
for EN or EN*.
(3)
Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
(4)
Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
(5)
CL includes probe and jig capacitance.
(6)
For DS90C032E propagation delay measurements are from 0V on the input waveform to the 50% point on the output (ROUT).
Copyright © 1998–2013, Texas Instruments Incorporated
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