AD9786BSVRL datasheet(24/56 Pages) AD

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AD9786

Rev. B | Page 24 of 56

Table 16.

DCLKCRC(05)

Bit

Direction

Default

Description

DATAADJ[3:0]

[7:4]

0000

DATACLK offset (twos complement representation)

0111: +7

0000: 0

1000: −8

MODSYNC

0: Channel data rate clock synchronizer mode

1: State machine clock synchronizer mode

fS/8

fS/4

fS/2

000

001

+1/√2

–1

010

–1

011

–1/√2

–1

100

–1

101

–1/√2

–1

110

–1

MODADJ[2:0]

[2:0]

000

111

+1/√2

–1

Modulator coefficient offset

Table 17.

VERSION(0D)

Bit

Direction

Default

Description

VERSION[3:0]

[3:0]

Hardware version identifier

Table 18.

CALMEMCK(OE)

Bit

Direction

Default

Description

CALMEM

[5:4]

Calibration memory

00: Uncalibrated

01: Self-calibration

10: Factory calibration

11: User input

CALCKDIV[2:0]

[2:0]

Calibration clock divide ratio from channel data rate

000: /32

001: /64

110: /2048

111: /4096

Table 19.

MEMRDWR(OF)

Bit

Direction

Default

Description

CALSTAT

0: Self-calibration cycle not complete

1: Self-calibration cycle complete

CALEN

1: Self-calibration in progress

XFERSTAT

0: Factory memory transfer not complete

1: Factory memory transfer complete

XFEREN

1: Factory memory transfer in progress

SMEMWR

1: Write static memory data from external port

SMEMRD

1: Read static memory to external port

FMEMRD

1: Read factory memory data to external port

UNCAL

1: Use uncalibrated

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