DOC7707 datasheet(193/307 Pages) ETC1

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193

7707F–AVR–11/10

AT90USB82/162

19.9

Registers description

19.9.1

USB general registers

• 7 – USBE: USB macro Enable Bit

Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the

USB transceiver and to disable the USB controller clock inputs.

• 6 – Reserved

The value read from this bit is always 0. Do not set this bit.

• 5 – FRZCLK: Freeze USB Clock Bit

Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power

consumption. Clear to enable the clock inputs.

• 4-0 – Reserved

The value read from these bits is always 0. Do not set these bits.

• 7 – DPACC: DPRAM Direct Access Bit

Set this bit to directly read the content the Dual-Port RAM (DPR) data through the UEDATX or

UPDATX registers. See Section 19.6, page 190 for more details.

Clear this bit for normal operation and access the DPR through the endpoint FIFO.

• 6-0 – Reserved

The value read from these bits is always 0. Do not set these bits.

Bit

5432

USBE

FRZLK

--USBCON

Read/Writ

R/W

RRR

Initial Val-

1000

Bit

76543210

DPACC

-------UDPADDH

Read/Wr

ite

R/W

RRRRRRR

Initial

Value

00000000

Bit

432

DPADD7:0

UDPADDL

Read/Writ

R/W

Initial Val-

000

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