DOC7707 datasheet(190/307 Pages) ETC1

190 / 307 page

190

7707F–AVR–11/10

AT90USB82/162

19.5

Power modes

19.5.1

Idle mode

In this mode, the CPU core is halted (CPU clock stopped). The Idle mode is taken wether the

USB controller is running or not. The CPU can wake up on any USB interrupts.

19.5.2

Power down

In this mode, the oscillator is stopped and halts all the clocks (CPU and peripherals). The USB

controller “wakes up” when:

• the WAKEUPI interrupt is triggered (single asynchronous interrupt)

19.5.3

Freeze clock

The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which

freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the fol-

lowing registers:

• USBCON,

• DPRAM direct access registers (DPADD7:0, UEDATX)

• UDCON (detach, ...)

•UDINT

•UDIEN

Moreover, when FRZCLK is set, only the asynchronous interrupt may be triggered :

• WAKEUPI

19.6

Memory management

The controller does only support the following memory allocation management.

The reservation of an Endpoint can only be made in the increasing order (Endpoint 0 to the last

Endpoint). The firmware shall thus configure them in the same order.

The reservation of an Endpoint “ki” is done when its ALLOC bit is set. Then, the hardware allo-

cates the memory and insert it between the Endpoints “ki-1” and “ki+1”. The “ki+1” Endpoint

memory “slides” up and its data is lost. Note that the “k

i+2” and upper Endpoint memory does not

slide.

Clearing an Endpoint enable (EPEN) does not clear either its ALLOC bit, or its configuration

(EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear ALLOC. Then, the

“k

i+1” Endpoint memory automatically “slides” down. Note that the “ki+2” and upper Endpoint

memory does not slide.

The following figure illustrates the allocation and reorganization of the USB memory in a typical

example:

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