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ADSP-BF607 Datasheet(PDF) 39 Page - Analog Devices

Part # ADSP-BF607
Description  Blackfin Dual Core Embedded Processor
PDF  112 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF607 Datasheet(HTML) 39 Page - Analog Devices

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Rev. 0
|
Page 39 of 112
|
June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DMC0_DQ13
I/O
B
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data 13.
Notes: No notes.
DMC0_DQ14
I/O
B
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data 14.
Notes: No notes.
DMC0_DQ15
I/O
B
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data 15.
Notes: No notes.
DMC0_LDM
I/O
B
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data Mask for Lower Byte.
Notes: No notes.
DMC0_LDQS
I/O
C
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data Strobe for Lower Byte.
Notes: For LPDDR, a 100k ohm pull-down
resistor is required.
DMC0_LDQS
I/O
C
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data Strobe for Lower Byte
(complement).
Notes: For single ended DDR2, connect to
VREF_DMC. For LPDDR, leave
unconnected.
DMC0_ODT
I/O
B
none
none
none
none
none
VDD_DMC
Desc: DMC0 On-die termination.
Notes: For LPDDR, leave unconnected.
DMC0_RAS
I/O
B
none
none
none
none
none
VDD_DMC
Desc: DMC0 Row Address Strobe.
Notes: No notes.
DMC0_UDM
I/O
B
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data Mask for Upper Byte.
Notes: No notes.
DMC0_UDQS
I/O
C
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data Strobe for Upper Byte.
Notes: For LPDDR, a 100k ohm pull-down
resistor is required.
DMC0_UDQS
I/O
C
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data Strobe for Upper Byte
(complement).
Notes: For single ended DDR2, connect to
VREF_DMC. For LPDDR, leave
unconnected.
DMC0_WE
I/O
B
none
none
none
none
none
VDD_DMC
Desc: DMC0 Write Enable.
Notes: No notes.
GND
g
na
none
none
none
none
none
na
Desc: Ground.
Notes: No notes.
JTG_EMU
I/O
A
none
none
none
none
none
VDD_EXT
Desc: Emulation Output.
Notes: No notes.
JTG_TCK
I/O
na
pd
none
none
none
none
VDD_EXT
Desc: JTG Clock.
Notes: Functional during reset.
JTG_TDI
I/O
na
pu
none
none
none
none
VDD_EXT
Desc: JTG Serial Data Input.
Notes: Functional during reset.
JTG_TDO
I/O
A
none
none
none
none
none
VDD_EXT
Desc: JTG Serial Data Output.
Notes: Functional during reset, three-
state when JTG_TRST is asserted.
JTG_TMS
I/O
na
pu
none
none
none
none
VDD_EXT
Desc: JTG Mode Select.
Notes: Functional during reset.
JTG_TRST
I/O
na
pd
none
none
none
none
VDD_EXT
Desc: JTG Reset.
Notes: Functional during reset.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name
Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes



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