FG484 datasheet(155/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-141

Table 2-209 • FIFO

Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and

A3PE3000L

Parameter

Description

–1

Std.

Units

tENS

REN_B, WEN_B Setup Time

1.46

1.71

tENH

REN_B, WEN_B Hold Time

0.02

tBKS

BLK_B Setup Time

0.40

0.47

tBKH

BLK_B Hold Time

0.00

tDS

Input Data (DI) Setup Time

0.19

0.23

tDH

Input Data (DI) Hold Time

0.00

tCKQ1

Clock HIGH to New Data Valid on DO (flow-through)

2.50

2.93

tCKQ2

Clock HIGH to New Data Valid on DO (pipelined)

0.95

1.11

tRCKEF

RCLK HIGH to Empty Flag Valid

1.82

2.14

tWCKFF

WCLK HIGH to Full Flag Valid

1.73

2.03

tCKAF

Clock HIGH to Almost Empty/Full Flag Valid

6.56

7.71

tRSTFG

RESET_B LOW to Empty/Full Flag Valid

1.79

2.11

tRSTAF

RESET_B LOW to Almost Empty/Full Flag Valid

6.49

7.63

tRSTBQ

RESET_B LOW to Data Out LOW on DO (flow-through)

0.98

1.15

RESET_B LOW to Data Out LOW on DO (pipelined)

0.98

1.15

tREMRSTB

RESET_B Removal

0.30

0.36

tRECRSTB

RESET_B Recovery

1.59

1.87

tMPWRSTB

RESET_B Minimum Pulse Width

0.59

0.67

tCYC

Clock Cycle Time

5.39

6.20

FMAX

Maximum Frequency for FIFO

185

161

MHz

Note:

For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

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