AD5247BKSZ100-R2 datasheet(5/20 Pages) AD

5 / 20 page

Data Sheet

AD5247

Rev. F | Page 5 of 20

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

DYNAMIC CHARACTERISTICS6, 8

Bandwidth –3 dB

RAB = 10 kΩ/50 kΩ/100 kΩ,

code = 0x40

600/100/40

kHz

Total Harmonic Distortion

THDW

VA =1 V rms, f = 1 kHz, RAB = 10 kΩ

0.05

VW Settling Time (10 kΩ/50 kΩ/100 kΩ)

VA = 5 V ±1 LSB error band

µs

Resistor Noise Voltage Density

eN_WB

RWB = 5 kΩ, RS = 0

nV/√Hz

Typical specifications represent average readings at 25°C and VDD = 5 V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

VA = VDD, wiper (VW) = no connect.

INL and DNL are measured at VW, with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.

Guaranteed by design, not subject to production test.

PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

All dynamic characteristics use VDD = 5 V.

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, −40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter1, 2, 3

Symbol

Min

Typ4

Max

Unit

SCL Clock Frequency

fSCL

400

kHz

Bus Free Time Between Stop and Start, tBUF

1.3

µs

Hold Time (Repeated Start), tHD;STA5

0.6

µs

Low Period of SCL Clock, tLOW

1.3

µs

High Period of SCL Clock, tHIGH

0.6

µs

Setup Time for Repeated Start Condition, tSU;STA

0.6

µs

Data Hold Time, tHD;DAT

0.9

µs

Data Setup Time, tSU;DAT

100

Fall Time of Both SDA and SCL Signals, tF

300

Rise Time of Both SDA and SCL Signals, tR

300

Setup Time for Stop Condition, tSU;STO

t10

0.6

µs

Specifications apply to all parts.

Guaranteed by design, not subject to production test.

See timing diagrams (Figure 2, Figure 33, and Figure 34) for locations of measured values.

Typical specifications represent average readings at 25°C and VDD = 5 V.

After this period, the first clock pulse is generated.

t10

SCL

SDA

Figure 2. I2C Interface, Detailed Timing Diagram

AD5247BKSZ100-R2 Datasheet(PDF) 5 Page - Analog Devices

AD5247BKSZ100-R2 Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL