TLV2556IPWR datasheet(8/37 Pages) TI

8 / 37 page

TLV2556

SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002

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timing characteristics over recommended operating free-air temperature range, VREF+ = 5 V, SCLK

frequency = 15 MHz, VCC = 5 V, load = 25 pF (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

tw1

Pulse duration I/O CLOCK high or low

26.7

100000

tsu1

Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38)

th1

Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38)

tsu2

Setup time CS low before 1st rising I/O CLOCK edge

(see Note 7 and Figure 39)

th2

Hold time CS pulse duration high time (see Figure 39)

100

th3

Hold time CS low after last I/O CLOCK falling edge (see Figure 39)

th4

Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40)

th5

Hold time CS high after EOC rising edge when CS is toggled (see Figure 43)

th6

Hold time CS high after INT falling edge (see Figure 43)

th7

Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is

held low (see Figure 44)

Delay time CS falling edge to DATA OUT valid

Load = 25 pF

td1

Delay time CS falling edge to DATA OUT valid

(MSB or LSB) (see Figure 37)

Load = 10 pF

td2

Delay time CS rising edge to DATA OUT high impedance (see Figure 37)

td3

Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40)

td4

Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41)

td5

Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion

1.5

µs

td6

Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41)

MAX(tconv)

td7

Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB

1st (see Figure 42)

td9

Delay time I/O CLOCK high to INT rising edge when CS is held low

(see Figure 44)

tt1

Transition time I/O CLOCK (see Note 7 and Figure 40)

µs

tt2

Transition time DATA OUT (see Figure 40)

tt3

Transition time INT/EOC, CL at 7 pF (see Figures 41 and 42)

2.4

tt4

Transition time DATA IN, CS

µs

tcyc

Total cycle time (sample, conversion and delays) (see Note 7)

MAX(tconv) + I/O

period

(8/12/16 CLKs)

µs

Source impedance = 25

Ω

600

Channel acquisition time (sample), at 1 k

Ω

Source impedance = 100

Ω

650

tsample

Channel acquisition time (sam le), at 1 k

Ω

(see Note 7)

Source impedance = 500

Ω

700

Source impedance = 1 K

Ω

1000

NOTE 7: I/O CLOCK period = 8

[1/(I/O CLOCK frequency)] or 12 [1/(I/O CLOCK frequency)] or 16 [1/(I/O CLOCK frequency)] depends

on I/O format selected.

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