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DAC8534IPW Datasheet(PDF) 4 Page - Texas Instruments

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Part # DAC8534IPW
Description  Quad Channel, Low Power, 16-Bit, Serial Input DIGITAL-TO-ANALOG CONVERTER
PDF  24 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC8534IPW Datasheet(HTML) 4 Page - Texas Instruments

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DAC8534
4
SBAS254D
www.ti.com
SERIAL WRITE OPERATION
SCLK
1
24
SYNC
D
IN
DB23
DB0
DB23
t
8
t
3
t
2
t
7
t
4
t
5
t
6
t
1
t
9
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNITS
t1(3)
SCLK Cycle Time
IOVDD = AVDD = 2.7V to 3.6V
50
ns
IOVDD = AVDD = 3.6V to 5.5V
33
ns
t2
SCLK HIGH Time
IOVDD = AVDD = 2.7V to 3.6V
26
ns
IOVDD = AVDD = 3.6V to 5.5V
15
ns
t3
SCLK LOW Time
IOVDD = AVDD = 2.7V to 3.6V
22.5
ns
IOVDD = AVDD = 3.6V to 5.5V
13
ns
t4
SYNC Falling Edge to SCLK
IOVDD = AVDD = 2.7V to 3.6V
0
ns
Rising Edge Setup Time
IOVDD = AVDD = 3.6V to 5.5V
0
ns
t5
Data Setup Time
IOVDD = AVDD = 2.7V to 3.6V
5
ns
IOVDD = AVDD = 3.6V to 5.5V
5
ns
t6
Data Hold Time
IOVDD = AVDD = 2.7V to 3.6V
4.5
ns
IOVDD = AVDD = 3.6V to 5.5V
4.5
ns
t7
24th SCLK Falling Edge to
IOVDD = AVDD = 2.7V to 3.6V
0
ns
SYNC Rising Edge
IOVDD = AVDD = 3.6V to 5.5V
0
ns
t8
Minimum SYNC HIGH Time
IOVDD = AVDD = 2.7V to 3.6V
50
ns
IOVDD = AVDD = 3.6V to 5.5V
33
ns
t9
24th SCLK Falling Edge to
IOVDD = AVDD = 2.7V to 5.5V
130
ns
SYNC Falling Edge
NOTES: (1) All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation
timing diagram, below. (3) Maximum SCLK frequency is 30MHz at IOVDD = AVDD = +3.6V to +5.5V and 20MHz at IOVDD = AVDD = +2.7V to +3.6V.
TIMING CHARACTERISTICS(1, 2)
AV
DD = +2.7V to +5.5V; all specifications –40°C to +105°C unless otherwise noted.
DAC8534



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