DSPIC33FJ12GP201TESLASHML datasheet(132/242 Pages) MICROCHIP

132 / 242 page

dsPIC33FJ12GP201/202

DS70264B-page 130

Preliminary

8. As a result of the second compare match event,

the OCxIF interrupt flag bit is set.

When the compare time base and the value in its

respective Timer Period register match, the TMRy

9. Steps 8 through 11 are repeated and a continuous

stream of pulses is generated, indefinitely. The

OCxIF flag is set on each OCxRS-TMRy compare

match event.

13.3

Pulse-Width Modulation Mode

Use the following steps when configuring the output

compare module for PWM operation:

Set the PWM period by writing to the selected

Timer Period register (PRy).

Set the PWM duty cycle by writing to the OCxRS

Write the OxCR register with the initial duty cycle.

Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin utilization.

Configure the output compare module for one of

two PWM operation modes by writing to the Out-

put Compare Mode bits, OCM<2:0> and

(OCxCON<2:0>).

Set the TMRy prescale value and enable the time base

by setting TON = 1 (TxCON<15>)

13.3.1

PWM PERIOD

The PWM period is specified by writing to PRy, the

Timer Period register. The PWM period can be

calculated using Equation 13-1:

EQUATION 13-1:

CALCULATING THE PWM

PERIOD

13.3.2

PWM DUTY CYCLE

Specify the PWM duty cycle is specified by writing to the

OCxRS register. The OCxRS register can be written to at

any time, but the duty cycle value is not latched into OCxR

until a match between PRy and TMRy occurs (i.e., the

period is complete). This provides a double buffer for the

PWM duty cycle and is essential for glitchless PWM

operation. In the PWM mode, OCxR is a read-only

Some important boundary parameters of the PWM duty

cycle include:

• If the Output Compare register, OCxR, is loaded

with 0000h, the OCx pin will remain low (0% duty

cycle).

• If OCxR is greater than PRy (Timer Period register),

the pin will remain high (100% duty cycle).

• If OCxR is equal to PRy, the OCx pin will be low

for one time base count value and high for all

other count values.

See Example 13-1 for PWM mode timing details.

Table 13-1 shows example PWM frequencies and

resolutions for a device operating at 10 MIPS.

EQUATION 13-2:

CALCULATION FOR MAXIMUM PWM RESOLUTION

Note:

The OCxR register should be initialized

before the output compare module is first

enabled. The OCxR register becomes a

read-only duty cycle register when the

module is operated in the PWM modes.

The value held in OCxR will become the

PWM duty cycle for the first PWM period.

The contents of the Output Compare

Secondary register, OCxRS, will not be

transferred into OCxR until a time base

period match occurs.

Note:

A PRy value of N will produce a PWM

period of N + 1 time base count cycles. For

example, a value of 7 written into the PRy

eight time base cycles.

PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)

PWM Frequency = 1/[PWM Period]

where:

(

)

Maximum PWM Resolution (bits) =

FCY

FPWM

log10

log10(2)

bits

DSPIC33FJ12GP201TE/ML Datasheet(PDF) 132 Page - Microchip Technology

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