TMS320DM6467CCUTAV datasheet(89/355 Pages) TI1

89 / 355 page

TMS320DM6467

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SPRS403H – DECEMBER 2007 – REVISED JUNE 2012

4.3

Clock Considerations

Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and

the Power and Sleep Controller (PSC). In addition, the System Module Video Clock Control (VIDCLKCTL),

TSIF Control (TSIFCTL), and Clock and Oscillator Control (CLKCTL) registers configure the clock sources

to the VPIF, TSIF, CRGEN peripherals, and the Auxiliary Oscillator.

The selected Video, TSIF, and CRGEN module input clocks are disabled using the System Module Video

Source Clock Disable (VSCLKDIS) register. Note: To ensure glitch-free operation, the clock should be

disabled before changing the clock source frequency or muxing via the VIDCLKCTL and TSIFCTL.

4.3.1

Clock Configurations after Device Reset

After device reset, the user is responsible for programming the PLL Controllers (PLLC1 and PLLC2) and

the Power and Sleep Controller (PSC) to bring the device up to the desired clock frequency and the

desired peripheral clock state (clock gating or not).

For additional power savings, some of the DM6467 peripherals support clock gating within the peripheral

boundary. For more details on clock gating and power saving features supported by a specific peripheral,

see the peripheral-specific reference/user's guides [listed/linked in the TMS320DM646x DMSoC

Peripherals Overview Reference Guide (literature number SPRUEQ0)].

4.3.1.1

Device Clock Frequency

The DM6467 defaults to PLL bypass mode. If the ROM bootloader is selected (BTMODE[3:0]

≠ 0100), the

bootloader code programs PLLC1 and PLLC2.

Section 4.4.1, Boot Modes discusses the different boot modes in more detail.

The user must adhere to the various clock requirements when programming the PLLC1 and PLLC2:

•

PLL multiplier and frequency ranges. For more details on PLL multiplier and frequency ranges, see

Section 7.5.1, PLL1 and PLL2.

4.3.1.2

Module Clock State

The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC).

Table 4-3 shows the default state of each module after a device-level global reset. The DM6467 device

has four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on

the definitions of the module states, the PSC, and PSC programming, see Section 7.3.5, Power and Sleep

Controller (PSC) and the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number

SPRUEP9).

Device Configurations

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