DM3725CBC datasheet(261/280 Pages) TI

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SWPS038-098

mmc1_clk

mmc1_cmd

mmc1_dat[n:0]

SD3

SD7

SD4

SD8

SD1

SD2

DM3730, DM3725

www.ti.com

SPRS685D

– AUGUST 2010 – REVISED JULY 2011

Table 6-132. MMC2 and MMC3 Interfaces Switching Characteristics

—Standard SDIO Mode(6)(7) (continued)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

tJ(clk)

Jitter standard deviation(3), output clock

200

tR(clk)

Rise time, output clock

tF(clk)

Fall time, output clock

tR(data)

Rise time, output data

tF(data)

Fall time, output data

SD5

td(CLKOH-CMD)

Delay time, mmcx_clk rising clock edge to

6.13

35.53

6.3

77.03

mmcx_cmd transition

SD6

td(CLKOH-DATx)

Delay time, mmcx_clk rising clock edge to

6.13

35.53

6.3

77.03

mmcx_dat[n:0](6) transition

(1) Related to the output mmcx_clk maximum and minimum frequency.

(2) P = output mmcx_clk period in ns

(3) The jitter probability density can be approximated by a Gaussian function.

(4) The X parameter is defined as follows:

CLKD

1 or Even

0.5

Odd

(trunk[CLKD/2]+1)/CLKD

All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual

(literature number SPRUGN4).

(5) The Y parameter is defined as follows:

CLKD

1 or Even

0.5

Odd

(trunk[CLKD/2])/CLKD

All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual

(literature number SPRUGN4).

(6) In mmcx, x is equal to 2 or 3. In mmcx_dat[n :0] is equal to 3 for mmc2 and 7 for mmc3.

(7) See Section 4.3.4, Processor Clocks.

Figure 6-75. MMC2 and MMC3 Interfaces

—Standard SDIO Mode—Data/Command Receive(1)

(1) In mmcx, x is equal to 2 or 3. In mmcx_dat[n:0] is equal to 3 for MMC2 and 7 for MMC3.

Timing Requirements and Switching Characteristics

261

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