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DM3725CBC Datasheet(PDF) 257 Page - Texas Instruments |
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DM3725CBC Datasheet(HTML) 257 Page - Texas Instruments |
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257 / 280 page ![]() SWPS038-100 mmc1_clk mmc1_cmd mmc1_dat[3:0] MMC3 MMC7 MMC4 MMC8 MMC1 MMC2 SWPS038-101 mmc1_clk mmc1_cmd mmc1_dat[3:0] MMC5 MMC5 MMC6 MMC6 MMC1 MMC2 DM3730, DM3725 www.ti.com SPRS685D – AUGUST 2010 – REVISED JULY 2011 Figure 6-71. MMC1 Interface —High-Speed MMC Mode—Data/Command Receive Figure 6-72. MMC1 Interface —High-Speed MMC Mode—Data/Command Transmit 6.6.8.1.6 MMC2 and MMC3 Interfaces —SDIO Identification Mode Table 6-125 and Table 6-126 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 6-73 and Figure 6-74). Table 6-124. MMC2 and MMC3 Interfaces Timing Conditions —SDIO Identification Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 10 ns tF Input signal fall time 10 ns Output Condition CLOAD Output load capacitance(1) 5 pF (1) Buffer strength configuration: LB0 = 0 Table 6-125. MMC2 and MMC3 Interfaces Timing Requirements —SDIO Identification Mode(1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC2 and MMC3 Interface (1.8-V IO) SD3 tsu(CMDV-CLKIH) Setup time, mmcx_cmd valid before 1198.4 1198.4 ns mmcx_clk rising clock edge SD4 th(CLKIH-CMDIV) Hold time, mmcx_cmd valid after mmcx_clk 1249.2 1249.2 ns rising clock edge (1) See Section 4.3.4, Processor Clocks. (2) In mmcx, x is equal to 2 or 3. Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 257 Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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