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DM3725CBC Datasheet(PDF) 253 Page - Texas Instruments |
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DM3725CBC Datasheet(HTML) 253 Page - Texas Instruments |
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253 / 280 page  DM3730, DM3725 www.ti.com SPRS685D – AUGUST 2010 – REVISED JULY 2011 Table 6-118. MMC1 Interface Timing Conditions —Standard MMC and MMC Identification Modes TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 3 ns tF Input signal fall time 3 ns Output Conditions CLOAD Output load capacitance(1) 30 pF (1) Buffer strength configuration: SPEEDCTRL = 1. Table 6-119. MMC1 Interface Timing Requirements —Standard MMC and MMC Identification Modes(2) (3) (4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 Interface (1.8-V IO) MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising 13.6 55.1 ns clock edge MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising 7.7 7.5 ns clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](1) valid before mmc1_clk 13.6 55.1 ns rising clock edge MMC8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](1) valid after mmc1_clk 7.7 7.5 ns rising clock edge MMC1 Interface (3.0-V IO) MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising 13.6 55.1 ns clock edge MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising 7.7 7.5 ns clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_dat[n:0](1) valid before mmc1_clk 13.6 55.1 ns rising clock edge MMC8 th(CLKIH-DATxIV) Hold time, mmc1_dat[n:0](1) valid after mmc1_clk 7.7 7.5 ns rising clock edge (1) In mmc1_dat[n:0], n is equal to 3. (2) Timing parameters are referred to output clock specified in Table 6-120. (3) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-120. (4) See Section 4.3.4, Processor Clocks. Table 6-120. MMC1 Interface Switching Characteristics —Standard MMC and MMC Identification Modes(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC Identification Mode MMC1 1/tc(clk) Frequency(1), output clk period 0.4 0.4 MHz MMC2 tW(clkH) Typical pulse duration, output clk high X(5)*PO(2) X(5)*PO(2) ns MMC2 tW(clkL) Typical pulse duration, output clk low Y(6)*PO(2) Y(6)*PO(2) ns tdc(clk) Duty cycle error, output clk 125 125 ns tJ(clk) Jitter standard deviation(3), output clk 200 200 ps Standard MMC Identification Mode MMC1 tc(clk) Frequency(1), output clk period 24 12 MHz MMC2 tW(clkH) Typical pulse duration, output clk high X(5)*PO(2) X(5)*PO(2) ns MMC2 tW(clkL) Typical pulse duration, output clk low Y(6)*PO(2) Y(6)*PO(2) ns tdc(clk) Duty cycle error, output clk 2083.3 4166.7 ps tJ(clk) Jitter standard deviation(3), output clk 200 200 ps MMC1 Interface (1.8-V IO) tR(clk) Rise time, output clk 10 10 ns Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 253 Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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