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DM3725CBC Datasheet(PDF) 250 Page - Texas Instruments

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Part # DM3725CBC
Description  Digital Media Processors
PDF  280 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DM3725CBC Datasheet(HTML) 250 Page - Texas Instruments

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SWPS038-094
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
HSSD3
HSSD7
HSSD4
HSSD8
HSSD1
HSSD2
SWPS038-095
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
HSSD5
HSSD5
HSSD6
HSSD6
HSSD1
HSSD2
DM3730, DM3725
SPRS685D
– AUGUST 2010 – REVISED JULY 2011
www.ti.com
Figure 6-65. MMC1 Interface
—High-Speed SD Mode—Data/Command Receive
Figure 6-66. MMC1 Interface
—High-Speed SD Mode—Data/Command Transmit
6.6.8.1.3 MMC1 Interface
—Standard SD Mode
Table 6-116 and Table 6-117 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 6-67 and Figure 6-68).
Table 6-115. MMC1 Interface Timing Conditions
—Standard SD Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
10
ns
tF
Input signal fall time
10
ns
Output Condition
CLOAD
Output load capacitance(1)
40
pF
(1) Buffer strength configuration: SPEEDCTRL = 1.
Table 6-116. MMC1 Interface Timing Requirements
—Standard SD Mode(1) (2) (4)
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
MMC1 Interface (1.8-V IO)
SD3
tsu(CMDV-CLKIH)
Setup time, mmc1_cmd valid before mmc1_clk rising
3.3
21.9
ns
clock edge
SD4
th(CLKIH-CMDIV)
Hold time, mmc1_cmd valid after mmc1_clk rising
18.1
36.7
ns
clock edge
SD7
tsu(DATxV-CLKIH)
Setup time, mmc1_dat[n:0](3) valid before mmc1_clk
3.3
21.9
ns
rising clock edge
SD8
th(CLKIH-DATxIV)
Hold time, mmc1_dat[n:0](3) valid after mmc1_clk
18.1
36.7
ns
rising clock edge
MMC1 Interface (3.0-V IO)
SD3
tsu(CMDV-CLKIH)
Setup time, mmc1_cmd valid before mmc1_clk rising
3.3
21.9
ns
clock edge
250
Timing Requirements and Switching Characteristics
Copyright
© 2010–2011, Texas Instruments Incorporated
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Product Folder Link(s): DM3730 DM3725



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