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DM3725CBC Datasheet(PDF) 246 Page - Texas Instruments |
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DM3725CBC Datasheet(HTML) 246 Page - Texas Instruments |
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246 / 280 page  DM3730, DM3725 SPRS685D – AUGUST 2010 – REVISED JULY 2011 www.ti.com • MMC2: – 1.8-V support – 8-bit without external transceiver – 4-bit with external transceiver allowing supporting 3-V peripherals. Transceiver direction control signals are multiplexed with the upper four data bits. • MMC3: – 1.8-V support – 8-bit without external transceiver 6.6.8.1.1 MMC1 Interface —SD Identification Modes Table 6-110 and Table 6-111 assume testing over the recommended operating conditions and electrical characteristic conditions below. Table 6-109. MMC1 Interface Timing Conditions —SD Identification Modes TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 10 ns tF Input signal fall time 10 ns Output Condition CLOAD Output load capacitance(1) 40 pF (1) Buffer strength configuration: LB0 = 0. Table 6-110. MMC1 Interface Timing Requirements —SD Identification Modes(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 Interface (1.8-V IO) SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising 1198.4 1198.4 ns clock edge SD4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising 1249.2 1249.2 ns clock edge MMC1 Interface (3.0-V IO) SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising 1198.4 1198.4 ns clock edge SD4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising 1249.2 1249.2 ns clock edge (1) Corresponding figures showing timing parameters are common with other interface modes. (See SD , HS SD modes). (2) See Section 4.3.4, Processor Clocks. Table 6-111. MMC1 Interface Switching Characteristics —SD Identification Modes(4) (7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SD Identification Mode SD1 tc(clk) Frequency(1), output clock period 0.4 0.4 MHz SD2 tW(clkH) Typical pulse duration, output clock high X(5)*PO(2) X(5)*PO(2) ns SD2 tW(clkL) Typical pulse duration, output clock low Y(6)*PO(2) Y(6)*PO(2) ns tdc(clk) Duty cycle error, output clock 125 125 ns tJ(clk) Jitter standard deviation(3), output clock 200 200 ps MMC1 Interface (1.8-V IO) tR(clk) Rise time, output clock 10 10 ns tF(clk) Fall time, output clock 10 10 ns 246 Timing Requirements and Switching Characteristics Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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