PCA9554_9554A

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Product data sheet

Rev. 9 — 19 March 2013

14 of 35

NXP Semiconductors

PCA9554; PCA9554A

[1]

[2]

Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.

[3]

The total current sourced by all I/Os must be limited to 85 mA.

10. Dynamic characteristics

[1]

[2]

[3]

Select inputs A0, A1, A2

LOW-level input voltage

0.5

-

0.8

V

HIGH-level input voltage

2.0

-

5.5

V

input leakage current

1-

1

A

Table 10.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 11.

Dynamic characteristics

Symbol

Parameter

Conditions

Standard-mode

Unit

Min

Max

Min

Max

SCL clock frequency

0

100

0

400

kHz

bus free time between a STOP and

START condition

4.7

-

1.3

-

s

hold time (repeated) START condition

4.0

-

0.6

-

s

set-up time for a repeated START

condition

4.7

-

0.6

-

s

set-up time for STOP condition

4.0

-

0.6

-

s

data hold time

0

-

0

-

s

data valid acknowledge time

[1]

0.3

3.45

0.1

0.9

s

data valid time

[2]

300

-

50

-

ns

data set-up time

250

-

100

-

ns

LOW period of the SCL clock

4.7

-

1.3

-

s

HIGH period of the SCL clock

4.0

-

0.6

-

s

rise time of both SDA and SCL signals

-

1000

300

ns

fall time of both SDA and SCL signals

-

300

300

ns

pulse width of spikes that must be

suppressed by the input filter

-

50

-

50

ns

Port timing

data output valid time

-

200

-

200

ns

data input set-up time

100

-

100

-

ns

data input hold time

1

-

1

-

s

Interrupt timing

valid time on pin INT

-4

-

4

s

reset time on pin INT

-4

-

4

s