PIC18F4680 datasheet(9/14 Pages) MICROCHIP

9 / 14 page

DS80202G-page 9

PIC18F2585/2680/4585/4680

28. Module: MSSP

When the MSSP is configured for SPI mode, the

Buffer Full Status bit, BF (SSPSTAT<0>), should

not be polled in software to determine when the

transfer is complete.

Work around

Copy the SSPSTAT register into a variable and

perform the bit test on the variable. In Example 5,

SSPSTAT is copied into the working register

where the bit test is performed.

EXAMPLE 5:

A second option is to poll the Master Synchronous

Serial Port Interrupt Flag bit, SSPIF (PIR1<3>).

This bit can be polled and will set when the transfer

is complete.

Date Codes that pertain to this issue:

All engineering and production devices.

29. Module: Reset

This version of silicon does not support the func-

tionality described in Note 1 of parameter D002 in

Section 27.1

“DC

Characteristics:

Supply

Voltage” of the Device Data Sheet. The RAM

content may be altered during a Reset event if the

following conditions are met.

• Device is accessing RAM.

• Asynchronous Reset (i.e., WDT, BOR or MCLR

occurs when a write operation is being

executed (start of a Q4 cycle).

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

30. Module: ECAN™ Technology

Under specific conditions, the first five bits of a

transmitted identifier may not match the value in

the Transmit Buffer ID register, TXBnSIDH. The

following conditions must exist for the corruption to

occur:

1. A transmit message must be pending.

2. The ECAN module must detect a Start-Of-

Frame (SOF) in the third bit of interframe

space.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

31. Module: ECAN™ Technology

The Error Interrupt Flag, ERRIF (PIR3<5>), may

not be able to clear in software after either of the

following counter registers exceeds 127.

• Transmit Error Counter Register TXERRCNT

• Receive Error Counter Register RXERRCNT

Work around

Monitor the EWARN (COMSTAT<0>) bit to deter-

mine if either the TXERRCNT or the RXERRCNT

exceeds 95 and clear the ERRIF flag before either

counter reaches 127.

Date Codes that pertain to this issue:

All engineering and production devices.

32. Module: ECAN™ Technology

Following an error on the bus, the ECAN module is

unable to switch from Listen Only mode directly to

Configuration mode.

Work around

Use the REQOP (CANCON<7:5>) bits to select

Normal mode as an intermediate step when

switching from Listen Only mode to Configuration

mode.

Date Codes that pertain to this issue:

All engineering and production devices.

loop_MSB:

MOVF

SSPSTAT, W

BTFSS

WREG, BF

BRA

loop_MSB

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