TIME (ns)

0.5

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

0

50

100

150

200

250

300

20 pF

10 pF

TIME (ns)

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

0

50

100

150

200

250

300

20 pF

10 pF

LMP8601/

LMP8601Q

0V

LMP8601, LMP8601-Q1

www.ti.com

SNOSAR2E – SEPTEMBER 2008 – REVISED MARCH 2013

symmetrical around 0V differential at the input pins. The signal at the output will follow this voltage difference

Example:

With 5V supply and a gain of 20x, a differential input signal of +10mV will result in 2.7V at the output pin.

similarly -10mV at the input will result in 2.3V at the output pin.

NOTE

The OFFSET pin has to be driven from a very low-impedance source (<10

Ω). This is

because the OFFSET pin internally connects directly to the resistive feedback networks of

the two gain stages. When the OFFSET pin is driven from a relatively large impedance

(e.g. a resistive divider between the supply rails) accuracy will decrease.

POWER SUPPLY DECOUPLING

In order to decouple the LMP8601/LMP8601Q from AC noise on the power supply, it is recommended to use a

the supply pins. In some cases an additional 10 µF bypass capacitor may further reduce the supply noise.

DRIVING SWITCHED CAPACITIVE LOADS

Some ADCs load their signal source with a sample and hold capacitor. The capacitor may be discharged prior to

being connected to the signal source. If the LMP8601/LMP8601Q is driving such ADCs the sudden current that

should be delivered when the sampling occurs may disturb the output signal. This effect was simulated with the

circuit shown in Figure 37 where the output is to a capacitor that is driven by a rail to rail square wave.

Figure 37. Driving Switched Capacitive Load

This circuit simulates the switched connection of a discharged capacitor to the LMP8601/LMP8601Q output. The

Figure 38. Capacitive Load Response at 3.3V

Figure 39. Capacitive Load Response at 5.0V

These figures can be used to estimate the disturbance that will be caused when driving a switched capacitive

load. To minimize the error signal introduced by the sampling that occurs on the ADC input, an additional RC

filter can be placed in between the LMP8601/LMP8601Q and the ADC as illustrated in Figure 40.

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