TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I

VOICE-BAND ANALOG INTERFACE CIRCUITS

SLAS017F − MARCH 1988 − REVISED MAY 1995

16

POST OFFICE BOX 655303

The TLC32044 or TLC32045 can be operated in special test modes. These test modes are used by Texas

Instruments to facilitate testing of the device during manufacturing. They are not intended to be used in real

applications; however, they allow the filters in the A/D and D/A paths to be used without using the A/D and D/A

converters.

In normal operation, the nonusable (NU) terminals are left unconnected. These NU terminals are used by the

factory to speed up testing of the TLC32044 or TLC32045 analog interface circuits (AIC). When the device is

used in normal (non-test mode) operation, the NU terminal (terminal 1) has an internal pulldown to − 5 V.

Externally connecting 0 V or 5 V to terminal 1 puts the device in test-mode operation. Selecting one of the

possible test modes is accomplished by placing a particular voltage on certain terminals. A description of these

modes is provided in Table 2 and Figures 5 and 6.

Table 2. List of Test Modes

TEST

TERMINALS

D/A PATH TEST (TERMINAL 1 to 5 V)

A/D PATH TEST (TERMINAL 1 to 0)

TEST

TERMINALS

TEST FUNCTION

TEST FUNCTION

5

The low-pass switched-capacitor filter clock is brought out to

DR. This clock signal is normally internal.

The bandpass switched-capacitor filter clock is brought out to

DR. This clock signal is normally internal.

5

The low-pass switched-capacitor filter clock is brought out to

DR. This clock signal is normally internal.

The bandpass switched-capacitor filter clock is brought out to

DR. This clock signal is normally internal.

11

No change from normal operation. The EODX signal is

brought out to EODX.

The pulse that initiates the A/D conversion is brought out here.

This signal is normally internal.

3

The pulse that initiates the D/A conversion is brought out here.

No change from normal operation. The EODR signal is

brought out.

27 and 28

There are no test output signals provided on these terminals.

The outputs of the A/D path low-pass or bandpass filter

(depending upon control bit d2 − see AIC DX data word format

section) are brought out to these terminals. If the high-pass

section is inserted, the output will have a (sin x) / x droop. The

slope of the droop is determined by the ADC sampling

frequency, which is the high-pass section clock frequency

(see diagram of bandpass or low-pass filter test for receive

section). These outputs drive small (30-pF) loads.

15 and 16

D/A PATH LOW-PASS FILTER TEST: (WORD/BYTE) to − 5 V

15 and 16

TEST FUNCTION

The inputs of the D/A path low-pass filter are brought out to terminals 15 and 16. The D/A input to this filter is removed. If (sin x) / x

correction filter is inserted, the OUT + and OUT − signals have a flat response (see Figure 2). The common-mode range of these

inputs must not exceed

±0.5 V.

for communicating between DSP and AIC. Either of the path tests (D/A or A/D) can be performed simultaneously with the D/A low-pass filter test.

In this situation, WORD/BYTE must be connected to − 5 V, which initiates byte-mode communications.