CLVC2G126MDCUTEP datasheet(2/13 Pages) TI1

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1OE

2OE

SN74LVC2G126-EP

SCES856 – DECEMBER 2013

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Logic Diagram (Positive Logic)

ABSOLUTE MAXIMUM RATINGs

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VCC

Supply voltage range

–0.5

6.5

Input voltage range(2)

–0.5

6.5

Voltage range applied to any output in the high-impedance or power-off state (2)

–0.5

6.5

Voltage range applied to any output in the high or low state (2) (3)

–0.5

VCC + 0.5

IIK

Input clamp current

VI < 0

–50

IOK

Output clamp current

VO < 0

–50

Continuous output current

±50

Continuous current through VCC or GND

±100

Absolute maximum junction temperature range

–55

150

°C

Tstg

Storage temperature range

–65

150

°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

The value of VCC is provided in the recommended operating conditions table.

THERMAL INFORMATION

SN74LVC2G126-EP

THERMAL METRIC(1)

DCU

UNITS

8 PINS

θJA

Junction-to-ambient thermal resistance(2)

204.3

θJCtop

Junction-to-case (top) thermal resistance(3)

θJB

Junction-to-board thermal resistance(4)

°C/W

ψJT

Junction-to-top characterization parameter(5)

7.6

ψJB

Junction-to-board characterization parameter(6)

82.6

θJCbot

Junction-to-case (bottom) thermal resistance(7)

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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